SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2 Three-Phase Traction Inverter
  4. 3 Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. 4 Single Positive Isolated Output Voltage
  6. 5 Dual Positive and Negative Output Voltages
  7. 6 Dual Positive Output Voltages
  8. 7 Capacitor Selection
  9. 8 RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. 9 UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

12 PCB Layout Considerations

Minimal external components mean easier, more direct PCB routing occupying less PCB area. Proper PCB layout is important to achieve optimum electrical and thermal performance. Automotive systems taking advantage of the high-performance features offered by the UCC14240-Q1 are likely to use multi-layer PCB designs. It is recommended to plan for at least a four-layer PCB design with 2-ounce copper preferred. The following thought given in terms of component placement and routing priority should also be applied as best as possible.

  1. Place the 2.2-µF and 0.1-µF decoupling capacitors as close as possible to the input and output device pins with the 0.1-µF bypass capacitors closest to the IC pins. For the input, place the capacitor between pins 6, 7 (VIN) and pins 1, 2, 5, 8-18 (GNDP). For the isolated output, place the capacitor(s) between pin 28, 29 (VDD) and pins 19-27, 30-31, 35-36 (VEE). This location is of particular importance to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.
  2. Because the device does not have a thermal pad for heat-sinking, heat is extracted through the respective GND pins. Ensure that enough copper – preferably a connection to the ground plane – is present on GNDP and VEE pins for best heat-sinking.
  3. If space and layer count allow, it is also recommended to connect the VIN, GNDP, VDD, RLIM, and VEE pins to internal ground or power planes through multiple vias of adequate size. Alternatively, make traces for these nets as wide as possible to minimize losses.
  4. TI also recommends grounding the no-connect pins (NC) to their respective ground planes. For single output option pins 32 and 34, connect to VEE. This will allow more continuous ground planes and larger thermal mass for heat-sinking.
  5. A minimum of four layers is recommended to allow sufficient internal layer GND shielding and low thermal impedance vias connecting the top and bottom layers for heat sinking the UCC14240-Q1. Inner layers can be used to create a high-frequency, common-mode stitch capacitor between GNDP and VEE, which in turn mitigates radiated emissions. An example showing the design of an internal PCB stitch capacitor can be found in the UCC12050EVM-022 EVM User's Guide.
  6. Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane (VEE) on the PCB's outer layers. The effective creep-age and or clearance of the system will be reduced if the two ground planes have a lower spacing than that of the UCC14240-Q1 package.
  7. To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the UCC14240-Q1 device.

Additional PCB guidance can be found within the UCC14240EVM-052 User's Guide.