SLUP412 February   2022 LMG3522R030-Q1


  1. Introduction
  2. Comparing Different Technologies
  3. Advantages of Integrating the Driver With GaN FETs
  4. The GaN-Based 6.6-kW OBC Reference Design
  5. PFC Stage
  6. DC/DC Stage
  7. DC/DC Topology Selection
  8. Frequency Selection
  9. Core Loss
  10. 10Loss of ZVS
  11. 11Dead Time
  12. 12ISR Bandwidth
  13. 13Overall
  14. 14Resonant Tank Design
  15. 15Thermal Solution
  16. 16Layout Best Practices
  17. 17Control-Loop Considerations
  18. 18Conclusions
  19. 19References
  20. 20Important Notice

Loss of ZVS

While the CLLLC converter does an excellent job maintaining ZVS over a wide range of conditions, there are still many situations in which it cannot. Figure 7-2 shows several operating points that partially or even fully lose ZVS. The ability to maintain ZVS is complicated by the fact that a CLLLC converter uses frequency modulation as the primary control mechanism for maintaining output regulation. It turns out that most, if not all, of the conditions where the CLLLC converter loses ZVS are at a lighter load and at frequencies well above resonance (more on this later). The switching losses in these conditions will be proportional to that operating frequency. Fundamentally, if the operating frequency gets too high, the converter may overheat at a light load.