SLUP412 February   2022 LMG3522R030-Q1


  1. Introduction
  2. Comparing Different Technologies
  3. Advantages of Integrating the Driver With GaN FETs
  4. The GaN-Based 6.6-kW OBC Reference Design
  5. PFC Stage
  6. DC/DC Stage
  7. DC/DC Topology Selection
  8. Frequency Selection
  9. Core Loss
  10. 10Loss of ZVS
  11. 11Dead Time
  12. 12ISR Bandwidth
  13. 13Overall
  14. 14Resonant Tank Design
  15. 15Thermal Solution
  16. 16Layout Best Practices
  17. 17Control-Loop Considerations
  18. 18Conclusions
  19. 19References
  20. 20Important Notice

Advantages of Integrating the Driver With GaN FETs

Two types of parasitic inductance between the driver and the FET limit the ultra-fast switching performance of GaN FETs: the common source inductance (CSI) and the gate-loop inductance. Minimizing both parasitic elements will help achieve the best possible switching performance.

A completely discrete approach will result in a large CSI because of inductance contributions from the integrated circuit (IC) packages and the driver to FET routing distance on the printed circuit board (PCB). The result will cause slower turnon of the GaN FET, with increased losses. Most GaN FET manufacturers currently only offer packages with a separate Kelvin source connection to reduce the CSI. A discrete FET solution with an external gate driver will have a larger CSI compared to the integrated driver and GaN solution from TI (see Figure 3-1 through Figure 3-4).

GUID-20220324-SS0I-SFL1-WZMD-HSL6KDZGHJ4G-low.jpg Figure 3-1 Discrete GaN FET and driver.
GUID-20220218-SS0I-JLVD-PK76-CT2B3MCGZBKS-low.png Figure 3-2 Discrete GaN FET and equivalent circuit diagram.
GUID-20220218-SS0I-PCBQ-N5D2-SCGDQVLR2LNR-low.png Figure 3-3 TI GaN FET with integrated driver.
GUID-20220218-SS0I-999N-TXRH-ZHVJSF1JK8BQ-low.png Figure 3-4 TI GaN FET with equivalent circuit diagram.

Meanwhile, integrating the driver and GaN also minimizes the gate-loop inductance, helping reduce gate-loop ringing, mitigating crosstalk, and improving gate reliability [6][7][8].

Figure 3-5 shows the simulated turnon switching waveforms of the high-side FET in a GaN FET half bridge for two different CSI values (0 nH and 5 nH).

Figure 3-5 Simulated switching waveform for different CSI values.

Having the smallest possible CSI enables the GaN FET to turnon much faster, without causing any switch-node ringing. In addition, the turnon switching losses of the GaN FET are smaller with a lower CSI value, which helps improve system efficiency (see Figure 3-6).

Figure 3-6 Simulated turnon energy for different CSI values.

There is a similar effect for the parasitic gate-loop inductance. Figure 3-7 illustrates that the smaller the gate-loop inductance value, the smaller the energy required to turnon the GaN FET (2 nH and 10 nH).

Figure 3-7 Simulated turnon energy for different gate-loop inductance values.