SLUP412 February 2022 LMG3522R030-Q1
Two types of parasitic inductance between the driver and the FET limit the ultra-fast switching performance of GaN FETs: the common source inductance (CSI) and the gate-loop inductance. Minimizing both parasitic elements will help achieve the best possible switching performance.
A completely discrete approach will result in a large CSI because of inductance contributions from the integrated circuit (IC) packages and the driver to FET routing distance on the printed circuit board (PCB). The result will cause slower turnon of the GaN FET, with increased losses. Most GaN FET manufacturers currently only offer packages with a separate Kelvin source connection to reduce the CSI. A discrete FET solution with an external gate driver will have a larger CSI compared to the integrated driver and GaN solution from TI (see Figure 3-1 through Figure 3-4).
Figure 3-5 shows the simulated turnon switching waveforms of the high-side FET in a GaN FET half bridge for two different CSI values (0 nH and 5 nH).
Having the smallest possible CSI enables the GaN FET to turnon much faster, without causing any switch-node ringing. In addition, the turnon switching losses of the GaN FET are smaller with a lower CSI value, which helps improve system efficiency (see Figure 3-6).
There is a similar effect for the parasitic gate-loop inductance. Figure 3-7 illustrates that the smaller the gate-loop inductance value, the smaller the energy required to turnon the GaN FET (2 nH and 10 nH).