This example covers a hypothetical and uses the principles of high-power design to improve a high-power motor driver application. Note, this example serves to show that how the process is utilized and rest of the application note explains the theory that eventually results in the process used.

Consider the following example:

• In a 48-V system running at 20 A using the DRV835x, the system works as expected
• When increasing the current to 30 A, which is the target current, the system is consistently damaged
• This happens for all systems brought above the 30 A current level

Examining the givens, there is a fundamental problem with the system. In this context, the functions of the gate drive circuit must be verified as the next step in troubleshooting.

After going through the troubleshooting steps, the notable observations are:

• The nFAULT signal is exerted only after trying to switch the low side and looking at the criteria, a VGS fault occurred on the low side which means that the gate voltage is not rising to the expected voltage when the input low-side gate signal is switched
• Using a DMM, an impedance test on the low-side gate-to-source shows a couple of couple of ohms which indicates a short and damage
• The damage occurs primarily on a singular phase but some other phases have received damage depending on the system tested

The short between gate-to-source seems to indicate that voltage inductive spiking is the problem as an absolute maximum limit could have been exceeded. This is further supported by the lack of damage at a lower current level. In addition, if there is damage is primarily on a singular phase then this might indicate that the layout is not optimized and might be contributing to the problem.

With a goal to reduce the voltage spiking:

• The gate drive sink and source current were reduced in an attempt to limit the spiking by lowering the IDRIVE.
  • This allowed the system to survive at 30-A but the resulting rise and fall time of the VDS signal, and gates, were too slow for the application. If the rise and fall time were acceptable, then the issue would have been solved here.

• By using an oscilloscope probe on the low-side gate and source voltages at 20 A, the waveforms show there is negative voltage spiking on the low-side source that is close but does not exceed the absolute maximum limits defined in the DRV835x 100-V Three-Phase Smart Gate Driver data sheet.

  • This leads the assumption that these spikes get worse as the current increases and eventually exceed the absolute maximum ratings

With some indicators that negative spiking on the low-side source and gate is the problem, some solutions include:

• Add high-side source to low-side capacitors
• Add gate-to-GND diodes
• Increase bulk capacitance
• Analyze the layout around the phase that receives damage and improving it, notably GND and the sense resistor path

Evaluate the options that may fix the problem. To avoid a redesign of the board, its best to look for a change on the bill of materials or populate components that were previously depopulated.

• Because the footprints for the high-side drain to low-side source capacitors were present, but not populated, adding a capacitor fixed the problem without having to do a redesign and without lowering the gate drive current.

This application note breaks down the process into a development of troubleshooting guidelines, a library of external circuits, TI driver product features, or layout techniques to combat the volatile nature of higher power systems.