SNLU334 December   2023 DS320PR410

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  DS320PR410 5-Level I/O Control Inputs
    2. 2.2  DS320PR410 Modes of Operation
    3. 2.3  DS320PR410 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR410 Equalization Control
    5. 2.5  DS320PR410 RX Detect State Machine
    6. 2.6  DS320PR410 DC Gain Control
    7. 2.7  DS320PR410 EVM Global Controls
    8. 2.8  DS320PR410-RSC-EVM Downstream Devices Control
    9. 2.9  DS320PR410-RSC-EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)
  9. 3Implementation Results
    1. 3.1 Test Setup and Results
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6References

DS320PR410 SMBus or I2C Register Control Interface

Each DS320PR410 internal registers can be accessed through standard SMBus protocol. The DS320PR410 features one bank of channels, Channels 0–3. The SMBus secondary address pairs (one for each device) are determined at power up based on the configuration of the EQ0 / ADDR0 and EQ1 / ADDR1 pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

There are 16 unique SMBus secondary addresses that can be assigned to the device by placing external resistor straps on the EQ0 / ADDR0 and EQ1 / ADDR1 pins as shown in Table 3-3. When multiple DS320PR410 devices are on the same SMBus interface bus, each device must be configured with a unique SMBus secondary address.

Table 2-3 DS320PR410 SMBus Address Map
ADDR1 Pin Level ADDR0 Pin Level DS320PR410 7-Bit Address [HEX]
L0 L0 0x18
L0 L1 0x1A
L0 L2 0x1C
L0 L3 0x1E
L0 L4 Reserved
L1 L0 0x20
L1 L1 0x22
L1 L2 0x24
L1 L3 0x26
L1 L4 Reserved
L2 L0 0x28
L2 L1 0x2A
L2 L2 0x2C
L2 L3 0x2E
L2 L4 Reserved
L3 L0 0x30
L3 L1 0x32
L3 L2 0x34
L3 L3 0x36
L3 L4 Reserved