SNLU334 December   2023 DS320PR410

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  DS320PR410 5-Level I/O Control Inputs
    2. 2.2  DS320PR410 Modes of Operation
    3. 2.3  DS320PR410 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR410 Equalization Control
    5. 2.5  DS320PR410 RX Detect State Machine
    6. 2.6  DS320PR410 DC Gain Control
    7. 2.7  DS320PR410 EVM Global Controls
    8. 2.8  DS320PR410-RSC-EVM Downstream Devices Control
    9. 2.9  DS320PR410-RSC-EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)
  9. 3Implementation Results
    1. 3.1 Test Setup and Results
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6References

2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)

  1. Configure all devices to operate in the SMBus Secondary Mode by setting their MODE pins to the L2 level. This is accomplished by placing a shunt on J1 L2 location.
  2. Set a unique SMBus Secondary address for each device by placing shunts in the following arrangement:
    • On J15 connector, place shunts in L0 locations for all downstream devices (DS1, DS2, DS3, and DS4) to set the ADDR1 level for each downstream DS320PR410.
    • On J16 connector, place shunts in L0 location for DS1, L1 location for DS2, L2 location for DS3, and in L3 location for DS4 to set the ADDR0 level for each downstream DS320PR410.
    • On J27 connector, place shunts in L1 locations for all upstream devices (US1, US2, US3, and US4) to set the ADDR1 level for each upstream DS320PR410 device.
    • On J28 connector, place shunts in L0 location for US1, L1 location for US2, L2 location for US3, and in L3 location for US4 to set the ADDR0 level for each upstream DS320PR410.
    • The above arrangement sets the 7-bit SMBus secondary addresses of the DS320PR410 devices as:
      • DS1: 0x18
      • DS2: 0x1A
      • DS3: 0x1C
      • DS4: 0x1E
      • US1: 0x20
      • US2: 0x22
      • US3: 0x24
      • US4: 0x26
  3. Move shunts from pins 1-2 to pins 2-3 on J17-J24, J29-J36 to connect the dual function redriver pins to the SMBus / I2C bus. Please reference Table 3-7 for guidance on the dual function pins.
  4. Make sure all devices by pulling their PWDN pins to GND. This is accomplished by placing a shunt on J4 between pins 5-6 (PWDN and GND). Alternatively, for PCIe sideband signal control, the PWDN pins can be driven by PCIe Present (PRSNT1#) signal by leaving J4 open and placing a shunt across pins 1 and 2 of J6, or by inverted PCIe Reset (PERST#) signal by placing a shunt between pins 3-4 on J4 and by leaving J6 open.
  5. Select the appropriate adapter using J38 (shunt position 1-2 for USB2ANY or 2-3 for Aardvark). Please make sure that the correct shunt setting is selected for your adapter. Otherwise, there is risk of damage to the EVM.
  6. Connect a USB2ANY Adapter or Aardvark Adapter to J3 (Note that neither is not supplied with the DS320PR410-RSC-EVM).
  7. Install the latest SigCon Architect application and the DS320PR410 profile. Please contact a local FAE for download instructions.
  8. Plug the EVM into a PCIe x16 server motherboard slot. Make sure the motherboard is powered down before installing the EVM or configured for hot-plug operation.
  9. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
  10. Power-up the motherboard.
  11. Start the SigCon Architect application.
  12. Select the DS320PR410 Configuration Page and click the Apply box to enable the device profile. If necessary, edit the devices SMBus addresses in the Edit Device Addresses box, then click Apply.
  13. In the DS320PR410 High Level Page, select Block Diagram as shown in Figure 3-1.
  14. Select the desired EQ Settings.
  15. Select devices you want to apply the selected settings and click Apply to All Channels.
    Note: To observe the effects of programmed DS320PR410 EQ settings on PCIe lane performance (lane margin, BER, etc.), the PCIe link must be re-trained by toggling PERST# or by performing a warm reset (without removing power to the DS320PR410).
GUID-20231020-SS0I-1FKL-HC5W-7PL847RRLKKV-low.png Figure 2-1 SigCon Architect DS320PR410 High-Level Page