SNOU150D January   2018  – April 2025 LMG1020

 

  1.   1
  2. 1 Introduction
  3. 2 Description
    1. 2.1 Typical Applications
    2. 2.2 Features
  4. 3 General TI High Voltage Evaluation User Safety Guidelines
  5. 4 Safety and Precautions
  6. 5 Electrical Performance Specifications
  7. 6 EVM Operation Out-of-the-Box
  8. 7 EVM Schematic
  9. 8 EVM Kit Contents
  10. 9 Test Setup
    1. 9.1 Test Equipment
    2. 9.2 Recommended Test Setup
    3. 9.3 List of Test Points
    4. 9.4 List of Terminals
  11. 10Test Procedure
    1. 10.1 Nanosecond Pulse Measurements
    2. 10.2 Pulse Shortener
    3. 10.3 Shutdown Procedure
      1. 10.3.1 Components rating and DNPs
  12. 11Performance Data and Typical Characteristics
  13. 12EVM Assembly Drawing and PCB Layout
  14. 13List of Materials
  15. 14Trademarks
  16. 15Revision History

2.2 Features

The LMG1020 has the following features and specifications:

  • Single low-side ultra-fast driver for 5-V drive GaN and silicon FETs
  • Single 5-V supply
  • Schmitt-trigger type CMOS inputs for robustness
  • 2.5-ns typical, 4.5-ns max propagation delay
  • 400-ps typical rise/fall time
  • UVLO and over-temperature protection
  • Minimum package 0.8 x 1.2 WCSP minimizes gate loop inductance and maximizes power density

The LMG1020EVM also includes the SN74LVC1G08, a single 2-input positive AND gate which provides the following features:

  • Buffer for the LMG1020 input
  • Used to shorten input pulse width by using a R-C filter on one input of the AND gate (Figure 10-1)
  • Bypass the buffer by populating R3 with a 0-Ω resistor and removing R10 to disconnect the AND gate output.

The EVM also features a low ESL, 0.47-uF feed through capacitor (C4 in Figure 7-1)

  • Feed through structure makes distance to GND shorter and obtains low ESL
  • Low ESL to prevent ringing on VDD (5.4-V Recommended Max)
  • Can be substituted with a 0201 capacitor placed as close to the pins as possible