SPRACL9 May   2019 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , AM5K2E02 , AM5K2E04 , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   KeyStone Multicore Device Family Schematic Checklist
    1.     Trademarks
    2. 1 Introduction
    3. 2 Hardware Design Guide
    4. 3 Device Comparison
      1. 3.1 KeyStone II Devices
      2. 3.2 KeyStone I Devices
    5. 4 Power Management Solutions
    6. 5 Recommendations Specific to all KeyStone Devices
      1. 5.1 EVM vs Data Sheet
      2. 5.2 Critical Connections
        1. 5.2.1 Power
        2. 5.2.2 Clocking
        3. 5.2.3 LJCB Differential Clock Inputs
        4. 5.2.4 Clock Termination
        5. 5.2.5 Unused Clock Inputs
        6. 5.2.6 Reset
        7. 5.2.7 GPIO/Boot Configuration
        8. 5.2.8 JTAG and EMU
    7. 6 Peripherals
      1. 6.1 DDR3 Interface
        1. 6.1.1  EMIF16
        2. 6.1.2  SerDes
        3. 6.1.3  HyperLink
        4. 6.1.4  PCIe
        5. 6.1.5  SRIO
        6. 6.1.6  SGMII
        7. 6.1.7  MDIO
        8. 6.1.8  TSIP
        9. 6.1.9  I2C
        10. 6.1.10 SPI
        11. 6.1.11 UART
        12. 6.1.12 I/O Buffers and Termination
    8. 7 Recommendations Specific to KeyStone II Devices
      1. 7.1 Peripherals
        1. 7.1.1 USB
    9. 8 General Recommendations
      1. 8.1 Before You Begin
        1. 8.1.1 Documentation
        2. 8.1.2 Pinout
    10. 9 References

6.1 DDR3 Interface

  • Address, command, clock signals must be routed in fly by topology with VTT termination. Balanced T routing is not supported on DDR3 design for these devices.
  • It is recommended to use dedicated ZQ resistor of 240 Ω 1% to be connected to each SDRAM ZQ pin (cannot share pins).
  • Each respective address and command net should be end terminated using a resistor (in the range of 39 Ω to 49 Ω) and connected to VTT. The preferred resistor value is 39 Ω, 1%.
  • The clock nets shall be terminated with a series 39 Ω, 1% resistor to a 0.1 µF capacitor to DVDD15 (VDDq).
  • Each trace to the respective termination should be ≤ within 500 mils and the opposite side of the termination resistor should tie directly to the VTT rail.
  • The reference voltage must be derived from the VDDQ supply using a resistor divider using 1% resistors (this reference voltage can also be derived from VTT power supply, such as TPS51200). It must be decoupled at the divider and each VREF input. Proper routing isolation is also needed for the VREF signal to prevent noise coupling. Additionally, the VREF input pins cannot be attached to the VTT termination supply rail.
  • The DDRRESET is a LVCMOS signal using the VDDQ levels. This signal must have a pull down resistor.
  • The DDRSLRATE signals are LVCMOS signals at the DVDD18 voltage.
  • Follow the recommended length matching rules for address and command, control, clock and data lines.
  • The routing rules must be followed for each routing group as given in the DDR3 design requirements. Similarly, recommended trace spacing is required to manage crosstalk.
  • For Keystone-I devices, pay special attention to the sections that describe the impact of round trip delay and write leveling on routing.
  • For more information, see DDR3 design requirements for KeyStone devices.
  • For the KeyStone I hardware design guide, see the Hardware design guide for KeyStone I devices.
  • For the KeyStone II hardware design guide, see the Hardware design guide for KeyStone II devices.