DLPS249 December   2024 DLP991U

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 DMD Temperature Calculation
      1. 6.6.1 Off-State Thermal Differential (TDELTA_MIN)
      2. 6.6.2 On-State Thermal Differential (TDELTA_MAX)
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 DMD Die Temperature Sensing
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 DMD Power Supply Power-Up Procedure
      2. 7.4.2 DMD Power Supply Power-Down Procedure
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 PCB Design Standards
        2. 7.5.1.2 General PCB Routing
          1. 7.5.1.2.1 Trace Impedance and Routing Priority
          2. 7.5.1.2.2 Example PCB Layer Stack-Up
          3. 7.5.1.2.3 Trace Width, Spacing
          4. 7.5.1.2.4 Power and Ground Planes
          5. 7.5.1.2.5 Trace Length Matching
            1. 7.5.1.2.5.1 HSSI Input Bus Skew
            2. 7.5.1.2.5.2 Other Timing Critical Signals
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information

4 Pin Configuration and Functions

DLP991U FLV Package 321-Pin LGA Bottom ViewFigure 4-1 FLV Package 321-Pin LGA Bottom View
CAUTION:

To ensure reliable, long-term operation of the DLP991U DMD, it is critical to properly manage the layout and operation of the signals identified in the table below. For specific details and guidelines, refer to the PCB Design Requirements for TI DLP® Standard SST Digital Micromirror Devices.

Table 4-1 Package Pinout
PIN INPUT-OUTPUT(1) PIN DESCRIPTION TERMINATION TRACE LENGTH (mm)
NAME PAD ID
D_AP(0) E1 I High-Speed Differential Data Pair lane A0 Differential 100Ω 10.79289
D_AN(0) F2 I High-Speed Differential Data Pair lane A0 Differential 100Ω 10.7718
D_AP(1) J1 I High-Speed Differential Data Pair lane A1 Differential 100Ω 13.77059
D_AN(1) G1 I High-Speed Differential Data Pair lane A1 Differential 100Ω 13.75662
D_AP(2) A5 I High-Speed Differential Data Pair lane A2 Differential 100Ω 10.33756
D_AN(2) B6 I High-Speed Differential Data Pair lane A2 Differential 100Ω 10.3464
D_AP(3) K2 I High-Speed Differential Data Pair lane A3 Differential 100Ω 12.35641
D_AN(3) L1 I High-Speed Differential Data Pair lane A3 Differential 100Ω 12.33238
D_AP(4) B8 I High-Speed Differential Data Pair lane A4 Differential 100Ω 9.64012
D_AN(4) A7 I High-Speed Differential Data Pair lane A4 Differential 100Ω 9.64824
D_AP(5) A11 I High-Speed Differential Data Pair lane A5 Differential 100Ω 11.96008
D_AN(5) A9 I High-Speed Differential Data Pair lane A5 Differential 100Ω 11.95453
D_AP(6) R1 I High-Speed Differential Data Pair lane A6 Differential 100Ω 17.77003
D_AN(6) T2 I High-Speed Differential Data Pair lane A6 Differential 100Ω 17.73406
D_AP(7) W1 I High-Speed Differential Data Pair lane A7 Differential 100Ω 21.44439
D_AN(7) U1 I High-Speed Differential Data Pair lane A7 Differential 100Ω 21.43676
DCLK_AP P2 I High-Speed Differential Clock A Differential 100Ω 16.02177
DCLK_AN N1 I High-Speed Differential Clock A Differential 100Ω 16.01225
D_BP(0) A13 I High-Speed Differential Data Pair lane B0 Differential 100Ω 8.39128
D_BN(0) B12 I High-Speed Differential Data Pair lane B0 Differential 100Ω 8.39933
D_BP(1) P30 I High-Speed Differential Data Pair lane B1 Differential 100Ω 30.30779
D_BN(1) R31 I High-Speed Differential Data Pair lane B1 Differential 100Ω 30.30599
D_BP(2) B14 I High-Speed Differential Data Pair lane B2 Differential 100Ω 9.53143
D_BN(2) A15 I High-Speed Differential Data Pair lane B2 Differential 100Ω 9.52732
D_BP(3) A17 I High-Speed Differential Data Pair lane B3 Differential 100Ω 11.23296
D_BN(3) B16 I High-Speed Differential Data Pair lane B3 Differential 100Ω 11.23915
D_BP(4) B20 I High-Speed Differential Data Pair lane B4 Differential 100Ω 13.82456
D_BN(4) A21 I High-Speed Differential Data Pair lane B4 Differential 100Ω 13.82794
D_BP(5) N31 I High-Speed Differential Data Pair lane B5 Differential 100Ω 26.98275
D_BN(5) L31 I High-Speed Differential Data Pair lane B5 Differential 100Ω 26.99587
D_BP(6) G31 I High-Speed Differential Data Pair lane B6 Differential 100Ω 24.55442
D_BN(6) J31 I High-Speed Differential Data Pair lane B6 Differential 100Ω 24.51977
D_BP(7) B22 I High-Speed Differential Data Pair lane B7 Differential 100Ω 16.27286
D_BN(7) A23 I High-Speed Differential Data Pair lane B7 Differential 100Ω 16.29733
DCLK_BP A19 I High-Speed Differential Clock B Differential 100Ω 12.98251
DCLK_BN B18 I High-Speed Differential Clock B Differential 100Ω 12.98727
D_CP(0) AL7 I High-Speed Differential Data Pair lane C0 Differential 100Ω 18.55831
D_CN(0) AL5 I High-Speed Differential Data Pair lane C0 Differential 100Ω 18.57877
D_CP(1) AG1 I High-Speed Differential Data Pair lane C1 Differential 100Ω 23.81943
D_CN(1) AF2 I High-Speed Differential Data Pair lane C1 Differential 100Ω 23.79686
D_CP(2) AC1 I High-Speed Differential Data Pair lane C2 Differential 100Ω 26.31612
D_CN(2) AE1 I High-Speed Differential Data Pair lane C2 Differential 100Ω 26.32655
D_CP(3) AA1 I High-Speed Differential Data Pair lane C3 Differential 100Ω 24.97633
D_CN(3) AB2 I High-Speed Differential Data Pair lane C3 Differential 100Ω 24.98848
D_CP(4) AK10 I High-Speed Differential Data Pair lane C4 Differential 100Ω 17.76946
D_CN(4) AL9 I High-Speed Differential Data Pair lane C4 Differential 100Ω 17.75209
D_CP(5) AL15 I High-Speed Differential Data Pair lane C5 Differential 100Ω 14.23357
D_CN(5) AK14 I High-Speed Differential Data Pair lane C5 Differential 100Ω 14.22774
D_CP(6) AK18 I High-Speed Differential Data Pair lane C6 Differential 100Ω 12.92082
D_CN(6) AL17 I High-Speed Differential Data Pair lane C6 Differential 100Ω 12.93366
D_CP(7) AL19 I High-Speed Differential Data Pair lane C7 Differential 100Ω 12.23762
D_CN(7) AL21 I High-Speed Differential Data Pair lane C7 Differential 100Ω 12.21188
DCLK_CP AL13 I High-Speed Differential Clock C Differential 100Ω 14.80911
DCLK_CN AL11 I High-Speed Differential Clock C Differential 100Ω 14.80629
D_DP(0) AL23 I High-Speed Differential Data Pair lane D0 Differential 100Ω 8.81383
D_DN(0) AK22 I High-Speed Differential Data Pair lane D0 Differential 100Ω 8.81029
D_DP(1) AL25 I High-Speed Differential Data Pair lane D1 Differential 100Ω 10.2057
D_DN(1) AK24 I High-Speed Differential Data Pair lane D1 Differential 100Ω 10.21071
D_DP(2) AK26 I High-Speed Differential Data Pair lane D2 Differential 100Ω 11.97626
D_DN(2) AL27 I High-Speed Differential Data Pair lane D2 Differential 100Ω 11.97857
D_DP(3) V30 I High-Speed Differential Data Pair lane D3 Differential 100Ω 17.09379
D_DN(3) U31 I High-Speed Differential Data Pair lane D3 Differential 100Ω 17.05432
D_DP(4) AF30 I High-Speed Differential Data Pair lane D4 Differential 100Ω 12.2472
D_DN(4) AE31 I High-Speed Differential Data Pair lane D4 Differential 100Ω 12.23151
D_DP(5) W31 I High-Speed Differential Data Pair lane D5 Differential 100Ω 14.32509
D_DN(5) Y30 I High-Speed Differential Data Pair lane D5 Differential 100Ω 14.32262
D_DP(6) AB30 I High-Speed Differential Data Pair lane D6 Differential 100Ω 11.15985
D_DN(6) AA31 I High-Speed Differential Data Pair lane D6 Differential 100Ω 11.15796
D_DP(7) AD30 I High-Speed Differential Data Pair lane D7 Differential 100Ω 13.11281
D_DN(7) AC31 I High-Speed Differential Data Pair lane D7 Differential 100Ω 13.11248
DCLK_DP AG31 I High-Speed Differential Clock D Differential 100Ω 13.93058
DCLK_DN AH30 I High-Speed Differential Clock D Differential 100Ω 13.92796
LS_WDATA_P B26 I LVDS Data Differential 100Ω 10.90213
LS_WDATA_N A27 I LVDS Data Differential 100Ω 10.90334
LS_CLK_P B24 I LVDS CLK Differential 100Ω 11.06614
LS_CLK_N A25 I LVDS CLK Differential 100Ω 11.02884
LS_RDATA_A F24 O LVCMOS Output 2.03585
LS_RDATA_B D26 O LVCMOS Output 5.2634
LS_RDATA_C F30 O LVCMOS Output 9.57426
LS_RDATA_D C27 O LVCMOS Output 7.1452
AMUX_OUT E17 O Analog Test Mux 6.35517
DMUX_OUT E29 O Digital Test Mux 7.21573
DMD_EN_ARSTZ AE23, E27, Y4 I ARSTZ 17.5kΩ Pulldown 63.74499
TEMP_N E23 I Temp Diode N 3.21385
TEMP_P F22 I Temp Diode P 2.85542
VDD A29, A3, AA29, AB4, AD10, AD12, AD28, AD8, AE13, AE15, AF10, AF12, AF18, AF22, AF24, AF26, AF28, AF6, AH10, AH12, AH14, AH16, AH18, AJ1, AJ11, AJ21, AJ29, AJ31, AJ5, AK2, AL29, B4, C1, C13, C21, C29, C31, D12, D16, D18, D20, D24, D8, F10, F12, F16, F18, F20, F8, H16, H18, H20, H22, H24, H28, K4, L3, M4, N29, P28, P4, T28, T4, V28, V4, Y28 P Digital Core Supply Voltage Plane
VDDA AB28, AD14, AD16, AD18, AD22, AD24, AE19, AE27, AF20, AH20, AH24, D10, D14, F6, G11, G15, H10, H12, H14, H26, H8, K28 P HSSI Supply Voltage Plane
VRESET AF4, AG5, D6, E5 P Supply Voltage for Negative Bias of Micromirror reset signal Plane
VBIAS AD4, AE3, D4 P Supply Voltage for Positive Bias of Micromirror reset signal Plane
VOFFSET AD26, AE5, F26, F4, H4 P Supply voltage for HVCMOS logic, stepped up logic level Plane
VSS A1, AA3, AC29, AC3, AD20, AD6, AE11, AE17, AE21, AE25, AE29, AE7, AE9, AF14, AF16, AF8, AG11, AG13, AG15, AG17, AG19, AG21, AG23, AG25, AG27, AG29, AG3, AH2, AH26, AH4, AH6, AK30, AK4, AK8, AL3, C3, D2, D22, D28, D30, E11, E13, E15, E19, E21, E25, E3, E31, E7, F14, G13, G17, G19, G21, G23, G25, G27, G29, G3, G5, G7, G9, H2, H30, H6, J29, J3, K30, L29, M2, M28, M30, N3, R29, R3, T30, U29, U3, V2, W29, W3, Y2 G Ground Plane
VSSA AD2, AH22, AH28, AJ13, AJ15, AJ17, AJ19, AJ23, AJ25, AJ27, AJ3, AJ7, AJ9, AK12, AK16, AK20, AK28, AK6, B10, B2, B28, B30, C11, C15, C17, C19, C23, C25, C5, C7, C9, E9 G Ground Plane
N/C AA5, AA27, AC5, AC27, AG7, AG9, AH8, F28, J5, J27, L5, L27, N27, R27, N5, R5, U5, U27, W5, W27 NC No Connect
(1) I = Input, O = Output, P = Power, G = Ground, NC = No Connect