DLPS249 Data sheet

DLPS249 December 2024 DLP991U

PRODUCTION DATA

5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted)⁽¹⁾

PARAMETER		MIN	TYP	MAX	UNIT
Supply Voltages
V_DD	Supply voltage for LVCMOS core logic and low speed interface (LSIF)⁽²⁾	1.85	1.9	1.95	V
V_DDA	Supply voltage for high speed serial interface (HSSI) receivers⁽²⁾	1.85	1.9	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽²⁾⁽³⁾⁽⁴⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for micromirror electrode⁽²⁾	17.5	18	18.5	V
V_RESET	Supply voltage for micromirror electrode⁽²⁾	–14.5	–14	–13.5	V
\| V_DDA – V_DD \|	Supply voltage delta, absolute value⁽⁵⁾			0.3	V
\| V_BIAS – V_OFFSET \|	Supply voltage delta, absolute value⁽⁶⁾			10.5	V
\| V_BIAS – V_RESET \|	Supply voltage delta, absolute value			33	V
LVCMOS Input
V_IH	High level input voltage⁽²⁾ ⁽⁷⁾	0.7 × V_DD			V
V_IL	Low level input voltage⁽²⁾⁽⁷⁾			0.3 × V_DD	V
Low Speed Interface (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK)⁽⁹⁾	108	120	130	MHz
DCD_IN	LSIF duty cycle distortion (LS_CLK)	44%		56%
\| V_ID \|	LSIF differential input voltage magnitude ⁽⁹⁾	150	350	440	mV
V_LVDS	LSIF voltage⁽⁹⁾	575		1520	mV
V_CM	Common mode voltage⁽⁹⁾	700	900	1300	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance	80	100	120	Ω
High Speed Serial Interface (HSSI)
f_CLOCK	HSSI clock frequency (DCLK)⁽⁸⁾	1.8	1.8	1.8	GHz
DCD_IN	HSSI duty cycle distortion (DCLK)	44%	50%	56%
\| V_ID \| Data	HSSI differential input voltage magnitude Data Lane⁽⁸⁾	100	400	600	mV
\| V_ID \| CLK	HSSI differential input voltage magnitude Clock Lane⁽⁸⁾	300	400	600	mV
VCM_DC Data	Input common mode voltage (DC) Data Lane⁽⁸⁾	200	600	800	mV
VCM_DC CLK	Input common mode voltage (DC) Clk Lane⁽⁸⁾	200	600	800	mV
VCM_ACp-p	AC peak to peak (ripple) on common mode voltages of Data Lane and Clock Lane⁽⁸⁾			100	mV
Z_LINE	Line differential impedance (PWB/trace)		100		Ω
Z_IN	Internal differential termination resistance ( R_Xterm)	80	100	120	Ω
Environmental 410nm – 800nm (Visible Wavelengths)
T_ARRAY	Array temperature, long-term operational⁽¹⁰⁾⁽¹¹⁾⁽¹³⁾⁽¹⁶⁾	45		70⁽¹²⁾	°C
T_ARRAY	Array temperature, short-term operational 500 hour maximum⁽¹¹⁾⁽¹⁴⁾	10		45	°C
T_WINDOW	Window temperature, operational, TP2 and TP3	15		75	°C
T_{DELTA_MAX}	[maximum of TP2 or TP3] minus T_{MIN_ARRAY}⁽¹⁶⁾			5	°C
T_{DELTA_MIN}	[minimum of TP2 or TP3] minus T_{MAX_ARRAY}⁽¹⁶⁾	–30			°C
RH	Relative humidity (non-condensing)			95%
Solid State Illumination 410nm – 800nm (Visible Wavelengths)
ILL_UV	Illumination power at wavelengths < 410nm⁽¹⁰⁾⁽¹⁷⁾			10	mW/cm²
ILL_VIS	Illumination power at wavelengths ≥ 410nm and ≤ 800nm⁽¹⁵⁾⁽¹⁷⁾			60	W/cm²
ILL_IR	Illumination power at wavelengths > 800nm⁽¹⁷⁾			10	mW/cm²
ILL_BLU	Illumination power at wavelengths ≥ 410nm and ≤ 475nm⁽¹⁵⁾⁽¹⁷⁾			20	W/cm²
ILL_BLU1	Illumination power at wavelengths ≥ 410nm and ≤ 440nm⁽¹⁵⁾⁽¹⁷⁾			3.1	W/cm²
Environmental⁽¹⁸⁾ For Illumination Source 400nm – 420nm
T_ARRAY	Array temperature, long-term operational⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾⁽¹³⁾⁽¹⁶⁾	20		30	°C
T_WINDOW	Window temperature, operational, TP2 and TP3	10		30	°C
T_{DELTA_MAX}	[maximum of TP2 or TP3] minus T_{MIN_ARRAY}⁽¹⁶⁾			5	°C
T_{DELTA_MIN}	[minimum of TP2 or TP3] minus T_{MAX_ARRAY}⁽¹⁶⁾	–10			°C
RH	Relative humidity (non-condensing)			95%
Duty Cycle	Operating Landed Duty Cycle⁽²⁰⁾		50%
Illumination 400nm – 420nm⁽¹⁹⁾
ILL_UV	Illumination power at wavelengths < 400nm⁽¹⁰⁾⁽¹⁷⁾			10	mW/cm²
ILL_BLU2	Illumination power at wavelengths ≥ 400nm and ≤ 420nm⁽¹⁵⁾⁽¹⁷⁾			22.5	W/cm²

(1) Section 5.4 are applicable after the DMD is installed in the final product.

(2) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(3) All voltage values are with respect to the V_SS ground pins.

(4) V_OFFSET supply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than specified limit.

(6) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than specified limit.

(7) LVCMOS input pin is DMD_DEN_ARSTZ.

(8) See the high-speed serial interface (HSSI) timing requirements in Section 5.8.

(9) See the low-speed interface (LSIF) timing requirements in Section 5.8.

(10) Simultaneous exposure of the DMD to the maximum Section 5.4 for temperature and UV illumination will reduce device lifetime.

(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 6-1, and the package thermal resistances using the calculation.

(12) The maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 6.8.1 for a definition of micromirror landed duty cycle.

(13) Long-term is defined as the usable life of the device.

(14) Short-term is defined as the cumulative time over the usable life of the device.

(15) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature T_ARRAY.

(16) Refer to Section 6.6 for calculation examples.

(17) Refer to Section 6.7 for calculation examples.

(18) Optimal, long-term performance and optical efficiency of the digital micromirror device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty-cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.

(19) This is the illumination power density and illumination total power on the DMD and does not include illumination overfill of the DMD device outside the active array.

(20) Landed Duty Cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the opposite state (–12° or 12°). 50% equates to a 50/50 duty cycle where the mirror has been landed 50% in the on-state and 50% in the off-state. See Section 7.8 for more information on landed duty cycle.

DLP991U Maximum
Recommended Array Temperature—Derating Curve for 410nm–800nm (Visible Wavelengths)

Figure 5-1 Maximum Recommended Array Temperature—Derating Curve for 410nm–800nm (Visible Wavelengths)