DLPS249 December   2024 DLP991U

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 DMD Temperature Calculation
      1. 6.6.1 Off-State Thermal Differential (TDELTA_MIN)
      2. 6.6.2 On-State Thermal Differential (TDELTA_MAX)
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 DMD Die Temperature Sensing
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 DMD Power Supply Power-Up Procedure
      2. 7.4.2 DMD Power Supply Power-Down Procedure
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 PCB Design Standards
        2. 7.5.1.2 General PCB Routing
          1. 7.5.1.2.1 Trace Impedance and Routing Priority
          2. 7.5.1.2.2 Example PCB Layer Stack-Up
          3. 7.5.1.2.3 Trace Width, Spacing
          4. 7.5.1.2.4 Power and Ground Planes
          5. 7.5.1.2.5 Trace Length Matching
            1. 7.5.1.2.5.1 HSSI Input Bus Skew
            2. 7.5.1.2.5.2 Other Timing Critical Signals
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information
7.5.1.2.2 Example PCB Layer Stack-Up
Careful attention to the PCB layer design is required to meet system design requirements. Table 7-7 shows an example PCB stack-up. To maximize signal integrity of the high-speed differential signals that make up the HSSI DMD input interface, the differential signals are routed on the internal layers and referenced to solid ground planes. To further improve the signal integrity of the DMD board, Nelco N4000-13 SI is used as the dielectric material to improve the signal slew rate for better performance of the HSSI DMD Input Interface.
Table 7-7 Example PCB Layer Stack-Up
LAYER NUMBER LAYER NAME COPPER WEIGHT COMMENTS
1 Side A—Primary Components ½ oz (before plating) Top components, including power generation and data input connectors. Low frequency signals routing. Need copper fill (GND) plated up to 1oz. Impedance reference for layer #2
2 Signal (High-Frequency) ½ oz High-speed signal layer, high-speed differential data buses from input connector to DMD. Data lines are kept underneath ground pour on layer #1.
3 Ground ½ oz Solid ground plane (net GND) reference for signal layer #2, #4
4 Signal (High-Frequency) ½ oz High-speed signal layer, high-speed differential data buses from input connector to DMD
5 Ground ½ oz Solid ground plane (net GND) reference for signal layers #4, #6
6 Signal (High-Frequency) ½ oz High-speed signal layer, high-speed differential data buses from input connector to DMD
7 Ground ½ oz Solid ground plane (net GND) reference for signal layer #6, 8
8 Side B—DMD, Power Planes and Secondary Components ½ oz (before plating)1 DMD and escapes. Data input connectors. Primary split power planes for 1.8V, 3.3V, 10V, –14V, 18V. Discrete components if necessary. Low-frequency signals routing. Need copper fill plated up to 1oz.
  1. As noted in the DLP991U DMD mechanical ICD drawing, the DMD device pads are plated with 50–100 micro-inches electrolytic nickel under 30 micro-inches minimum electrolytic gold.