DLPS249 December   2024 DLP991U

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 DMD Temperature Calculation
      1. 6.6.1 Off-State Thermal Differential (TDELTA_MIN)
      2. 6.6.2 On-State Thermal Differential (TDELTA_MAX)
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 DMD Die Temperature Sensing
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 DMD Power Supply Power-Up Procedure
      2. 7.4.2 DMD Power Supply Power-Down Procedure
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 PCB Design Standards
        2. 7.5.1.2 General PCB Routing
          1. 7.5.1.2.1 Trace Impedance and Routing Priority
          2. 7.5.1.2.2 Example PCB Layer Stack-Up
          3. 7.5.1.2.3 Trace Width, Spacing
          4. 7.5.1.2.4 Power and Ground Planes
          5. 7.5.1.2.5 Trace Length Matching
            1. 7.5.1.2.5.1 HSSI Input Bus Skew
            2. 7.5.1.2.5.2 Other Timing Critical Signals
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information

Timing Requirements

Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOLPARAMETERTEST CONDITIONSMINTYPMAXUNIT
LVCMOS
trRise time (1)20% to 80% reference points25ns
tfFall time (1)80% to 20% reference points25ns
Low Speed Interface (LSIF)
trRise time (2)20% to 80% reference points450ps
tfFall time (2)80% to 20% reference points450ps
tsuSetup time(3)LS_WDATA valid before rising edge of LS_CLK (differential)1.5ns
thHold time (3)LS_WDATA valid after rising edge of LS_CLK (differential)1.5ns
High Speed Serial Interface (HSSI)
trRise time (4)from -A1 to A1 minimum eye height specification50100ps
tfFall time (4)from A1 to -A1 minimum eye height specification50100ps
See Figure 5-9 for rise time and fall time for LVCMOS.
See Figure 5-5 for rise time and fall time for LSIF.
See Figure 5-4  for setup and hold time for LSIF.
See Figure 5-10 for rise time and fall time for HSSI.

DLP991U
Equation 1. DLP991U
Equation 2. DLP991U

Figure 5-3 LSIF Waveform Requirements
DLP991U LSIF Timing RequirementsFigure 5-4 LSIF Timing Requirements
DLP991U LSIF Rise, Fall Time SlewFigure 5-5 LSIF Rise, Fall Time Slew
DLP991U LSIF Voltage RequirementsFigure 5-6 LSIF Voltage Requirements
DLP991U LSIF Equivalent InputFigure 5-7 LSIF Equivalent Input
DLP991U LVCMOS Input HysteresisFigure 5-8 LVCMOS Input Hysteresis
DLP991U LVCMOS Rise, Fall Time Slew RateFigure 5-9 LVCMOS Rise, Fall Time Slew Rate
DLP991U HSSI Waveform Requirements
Equation 3. DLP991U
Equation 4. DLP991U
Figure 5-10 HSSI Waveform Requirements
DLP991U HSSI Eye CharacteristicsFigure 5-11 HSSI Eye Characteristics
DLP991U HSSI CLK CharacteristicsFigure 5-12 HSSI CLK Characteristics