SBAA461 December   2020 ADC3541 , ADC3542 , ADC3543 , ADC3544 , ADC3641 , ADC3642 , ADC3643 , ADC3644 , ADC3660 , ADC3681 , ADC3682 , ADC3683

 

  1.   Trademarks
  2. 1Introduction
  3. 2Reduce Data Rates: Optimize Pin Count and Data Rate
    1. 2.1 Parallel CMOS
      1. 2.1.1 Parallel SDR
      2. 2.1.2 Parallel DDR
    2. 2.2 Serial CMOS
      1. 2.2.1 2 Wire
      2. 2.2.2 1 Wire
      3. 2.2.3 0.5 Wire
  4. 3Reduce Data Rates: Decimation
  5. 4Summary
  6. 5References

2.2 Serial CMOS

If reducing the CMOS data output resistor count (or pin count) is even more critical in your system, then using a serialized CMOS interface (DDR) may be an attractive choice. Similar to parallel CMOS, there are a few options to consider when using a serial CMOS interface.

To transmit all 14 bits within the time period of the sampling rate, the ADC output data must be transmitted at a faster rate (serialized), and we must provide this serialization frequency as an input to the ADC. Also, a frame clock is now generated by the ADC to encapsulate each 14 bit sample, so that we will know the beginning and end of each sample.