SBAA461 December   2020 ADC3541 , ADC3542 , ADC3543 , ADC3544 , ADC3641 , ADC3642 , ADC3643 , ADC3644 , ADC3660 , ADC3681 , ADC3682 , ADC3683

 

  1.   Trademarks
  2. 1Introduction
  3. 2Reduce Data Rates: Optimize Pin Count and Data Rate
    1. 2.1 Parallel CMOS
      1. 2.1.1 Parallel SDR
      2. 2.1.2 Parallel DDR
    2. 2.2 Serial CMOS
      1. 2.2.1 2 Wire
      2. 2.2.2 1 Wire
      3. 2.2.3 0.5 Wire
  4. 3Reduce Data Rates: Decimation
  5. 4Summary
  6. 5References

2.1 Parallel CMOS

Parallel CMOS output is the most common method of implementation for high-speed CMOS ADCs. However, there are different Parallel CMOS implementations, like SDR (Single Data Rate) and DDR (Dual Data Rate), and both have implications on either data rate or pin count. Due to the nature of the CMOS output, a series resistance is needed to control the current output and ensure signal integrity, so reducing the number of output pins will correspondingly reduce the amount of series resistors.