Product details

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 97 Architecture SAR SNR (dB) 74 ENOB (Bits) 12.8 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 97 Architecture SAR SNR (dB) 74 ENOB (Bits) 12.8 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • 14-bit 125 MSPS ADC
  • Noise floor: –153 dBFS/Hz
  • Ultra-low power with optimized power scaling: 97 mW/ch (125 MSPS)
  • Latency: 1 clock cycle
  • INL: ±1.5 LSB; DNL: ±0.5 LSB
  • Reference: external or internal
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • SDR/DDR and Serial CMOS interface
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral performance (fIN = 5 MHz):
    • SNR: 74.0 dBFS
    • SFDR: 85-dBc HD2, HD3
    • SFDR: 93-dBFS worst spur
  • Spectral performance (fIN = 70 MHz):
    • SNR: 70.6dBFS
    • SFDR: 79-dBc HD2, HD3
    • SFDR: 85-dBFS worst spur
  • 14-bit 125 MSPS ADC
  • Noise floor: –153 dBFS/Hz
  • Ultra-low power with optimized power scaling: 97 mW/ch (125 MSPS)
  • Latency: 1 clock cycle
  • INL: ±1.5 LSB; DNL: ±0.5 LSB
  • Reference: external or internal
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • SDR/DDR and Serial CMOS interface
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral performance (fIN = 5 MHz):
    • SNR: 74.0 dBFS
    • SFDR: 85-dBc HD2, HD3
    • SFDR: 93-dBFS worst spur
  • Spectral performance (fIN = 70 MHz):
    • SNR: 70.6dBFS
    • SFDR: 79-dBc HD2, HD3
    • SFDR: 85-dBFS worst spur

The ADC3544 device is a low-noise, ultra-low power, 14-bit, 125-MSPS, high-speed analog-to-digital converter (ADC). Designed for low power consumption, the device delivers a noise spectral density of –153 dBFS/Hz, combined with a good linearity and dynamic range. The ADC3544 offers IF sampling support, which make these devices an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 97 mW/ch at 125 MSPS, and the power consumption scales well with lower sampling rates.

The ADC3544 uses an SDR or DDR interface to output the data offering the lowest power digital interface, together with the flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40°C to 105⁰C.

The ADC3544 device is a low-noise, ultra-low power, 14-bit, 125-MSPS, high-speed analog-to-digital converter (ADC). Designed for low power consumption, the device delivers a noise spectral density of –153 dBFS/Hz, combined with a good linearity and dynamic range. The ADC3544 offers IF sampling support, which make these devices an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 97 mW/ch at 125 MSPS, and the power consumption scales well with lower sampling rates.

The ADC3544 uses an SDR or DDR interface to output the data offering the lowest power digital interface, together with the flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40°C to 105⁰C.

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Our ADC3660 family won the 2021 World Electronics Achievement Awards (WEAA) Product of the Year in the Amplifier/Data Conversion category.

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Technical documentation

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* Data sheet ADC3544 14-bit, 125-MSPS, Low Noise, Low Power ADC datasheet PDF | HTML 14 Dec 2020
Application note High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs 09 Dec 2020
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization PDF | HTML 08 Dec 2020
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020

Design & development

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Evaluation board

ADC3544EVM — ADC3544 evaluation module

The ADC354x evaluation module (EVM) is designed to evaluate the single channel variants of the ADC36xx family of high-speed analog-to-digital converters (ADCs), including the ADC3543 and the ADC3544. These ADCs have a configurable, serial or parallel, low-voltage CMOS (LVCMOS) data interface.
User guide: PDF | HTML
Not available on TI.com
GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (RSB) 40 Ultra Librarian

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