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ADC3644

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Dual-channel, 14-bit, 125-MSPS, low-noise, ultra-low-power analog-to-digital converter (ADC)

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Data sheet

ADC3644

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 164 Architecture SAR SNR (dB) 74 ENOB (Bits) 12.8 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 164 Architecture SAR SNR (dB) 74 ENOB (Bits) 12.8 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • Dual channel
  • 14-bit 125 MSPS ADC
  • Noise floor: –153 dBFS/Hz
  • Ultra-low power with optimized power scaling: 82 mW/ch (125 MSPS)
  • Latency: 1 clock cycle
  • 14-Bit, no missing codes
  • INL: ±1.5 LSB; DNL: ±0.5 LSB
  • Reference: external or internal
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • DDR and Serial CMOS interface
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral performance (fIN = 5 MHz):
    • SNR: 74.0 dBFS
    • SFDR: 90-dBc HD2, HD3
    • SFDR: 100-dBFS worst spur
  • Spectral performance (fIN = 70 MHz):
    • SNR: 72.5 dBFS
    • SFDR: 70-dBc HD2, HD3
    • SFDR: 85-dBFS worst spur
  • Dual channel
  • 14-bit 125 MSPS ADC
  • Noise floor: –153 dBFS/Hz
  • Ultra-low power with optimized power scaling: 82 mW/ch (125 MSPS)
  • Latency: 1 clock cycle
  • 14-Bit, no missing codes
  • INL: ±1.5 LSB; DNL: ±0.5 LSB
  • Reference: external or internal
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • DDR and Serial CMOS interface
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral performance (fIN = 5 MHz):
    • SNR: 74.0 dBFS
    • SFDR: 90-dBc HD2, HD3
    • SFDR: 100-dBFS worst spur
  • Spectral performance (fIN = 70 MHz):
    • SNR: 72.5 dBFS
    • SFDR: 70-dBc HD2, HD3
    • SFDR: 85-dBFS worst spur

The ADC3644 device is a low-noise, ultra-low power, 14-bit, 125-MSPS dual-channel, high-speed analog-to-digital converter (ADC). Designed for low power consumption, the device delivers a noise spectral density of –153 dBFS/Hz, combined with very good linearity and dynamic range. The ADC3644 offers IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 82 mW/ch at 125 MSPS, and power consumption scales well with lower sampling rates.

The ADC3644 use a DDR or a serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to 105⁰C.

The ADC3644 device is a low-noise, ultra-low power, 14-bit, 125-MSPS dual-channel, high-speed analog-to-digital converter (ADC). Designed for low power consumption, the device delivers a noise spectral density of –153 dBFS/Hz, combined with very good linearity and dynamic range. The ADC3644 offers IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 82 mW/ch at 125 MSPS, and power consumption scales well with lower sampling rates.

The ADC3644 use a DDR or a serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to 105⁰C.
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Our ADC3660 family won the 2021 World Electronics Achievement Awards (WEAA) Product of the Year in the Amplifier/Data Conversion category.

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Technical documentation

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Type Title Date
* Data sheet ADC3644 14-bit, 125-MSPS, Low-noise, Low Power Dual Channel ADC datasheet PDF | HTML 16 Mar 2020
Application note High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs 09 Dec 2020
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization PDF | HTML 08 Dec 2020
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020

Design & development

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Evaluation board

ADC3644EVM — ADC3644 evaluation module for dual-channel, 14-bit, 125-MSPS, low-noise, ultra-low-power ADC

The ADC3644 evaluation module (EVM) is a platform that demonstrates the performance of the ultra-low-power, high-linearity ADC3644. Onboard voltage regulation and flexible analog input options allow for easy evaluation for many different applications.

Interfacing to the TSW1400EVM (sold separately) (...)

User guide: PDF
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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