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High-speed ADCs (≥10 MSPS)
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ADC3542

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Single-channel, 14-bit, 25-MSPS, low-noise, ultra-low-power and low-latency ADC

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Data sheet

ADC3542

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 25 Resolution (Bps) 14 Number of input channels 1 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 46 Architecture SAR SNR (dB) 79 ENOB (Bps) 12.8 SFDR (dB) 97 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 25 Resolution (Bps) 14 Number of input channels 1 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 46 Architecture SAR SNR (dB) 79 ENOB (Bps) 12.8 SFDR (dB) 97 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • 14-bit 10/25/65 MSPS ADC
  • Noise floor: –155 dBFS/Hz
  • Ultra-low power with optimized power scaling: 35 mW (10 MSPS) to 84 mW (65 MSPS)
  • Latency: 1 clock cycle
  • INL: ±0.6 LSB; DNL: ±0.1 LSB
  • Reference: external or internal
  • Input Bandwidth: 900 MHz (3-dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • SDR/DDR and Serial CMOS interface
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral Performance (fIN = 10 MHz):
    • SNR: 79.0 dBFS
    • SFDR: 87 dBc HD2, HD3
    • SFDR: 99 dBFS Worst Spur
  • Spectral Performance (fIN = 64 MHz):
    • SNR: 78.0 dBFS
    • SFDR: 70 dBc HD2, HD3
    • SFDR: 91 dBFS Worst Spur
  • 14-bit 10/25/65 MSPS ADC
  • Noise floor: –155 dBFS/Hz
  • Ultra-low power with optimized power scaling: 35 mW (10 MSPS) to 84 mW (65 MSPS)
  • Latency: 1 clock cycle
  • INL: ±0.6 LSB; DNL: ±0.1 LSB
  • Reference: external or internal
  • Input Bandwidth: 900 MHz (3-dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • SDR/DDR and Serial CMOS interface
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral Performance (fIN = 10 MHz):
    • SNR: 79.0 dBFS
    • SFDR: 87 dBc HD2, HD3
    • SFDR: 99 dBFS Worst Spur
  • Spectral Performance (fIN = 64 MHz):
    • SNR: 78.0 dBFS
    • SFDR: 70 dBc HD2, HD3
    • SFDR: 91 dBFS Worst Spur

The ADC3541, ADC3542 and ADC3543 (ADC354x) family of devices are low-noise, ultra-low power, 14-bit, 10 to 65-MSPS, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz. The ADC354x offers great dc precision together with IF sampling support, which make these devices an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 79 mW at 65 MSPS, and the power consumption scales very well with lower sampling rates.

The ADC354x uses an SDR, DDR or a serial CMOS interface to output the data offering the lowest power digital interface, together with the flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40°C to +105⁰C.

The ADC3541, ADC3542 and ADC3543 (ADC354x) family of devices are low-noise, ultra-low power, 14-bit, 10 to 65-MSPS, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz. The ADC354x offers great dc precision together with IF sampling support, which make these devices an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 79 mW at 65 MSPS, and the power consumption scales very well with lower sampling rates.

The ADC354x uses an SDR, DDR or a serial CMOS interface to output the data offering the lowest power digital interface, together with the flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40°C to +105⁰C.
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Our ADC3660 family won the 2021 World Electronics Achievement Awards (WEAA) Product of the Year in the Amplifier/Data Conversion category.

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Technical documentation

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Type Title Date
* Data sheet ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC datasheet (Rev. C) PDF | HTML 15 Dec 2022
EVM User's guide ADC354xEVM User's Guide (Rev. A) PDF | HTML 24 Jan 2023
Application note High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs 09 Dec 2020
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization PDF | HTML 08 Dec 2020
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020

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DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
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ADC35xx TINA-TI Reference Design

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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