SBAA531 November   2021 ADS8860 , ADS8862 , ADS8881 , ADS9110 , ADS9224R

 

  1.   Trademarks
  2. 1Introduction
  3. 2 Internal Topology of SAR ADC Model
    1. 2.1  Sample and Hold
    2. 2.2  Sample and Hold Timing
    3. 2.3  Reference Transients
    4. 2.4  Bandwidth Modeling
    5. 2.5  Noise Modeling
    6. 2.6  Reference Droop and Reference Noise Errors
    7. 2.7  Gain, Offset, and Input Leakage Modeling
    8. 2.8  Differential input behavior
    9. 2.9  ESD Protection Diodes and Parasitic Capacitance
    10. 2.10 Summary of Parameters
    11. 2.11 Summary of Model Pins
  4. 3Downloading and Using PSpice® Example Projects From Web
    1. 3.1 Selecting the Amplifier and Optimizing the RC Circuit
    2. 3.2 Worst-Case Settling by Adjusting the Reset Capacitor
    3. 3.3 Verification of Reference Droop
    4. 3.4 System Noise Verification
    5. 3.5 Gain, Offset, and Input Leakage Verification
  5. 4Summary

3.2 Worst-Case Settling by Adjusting the Reset Capacitor

As mentioned in Section 2.2, the internal sample and hold is reset at the end of the sample and hold period using the reset capacitor Cres. This capacitor is typically set to 10% of the sample and hold value so that the voltage droop at the end of the conversion (hold) period is approximately 10% of the hold value. For example, if Csh is 55 pF, than Cres is typically set to 5.5 pF. In this case if the held voltage is 5 V it will be reset to 4.5 V at the end conversion period. This circuit models the real-world behavior of many modern SAR ADCs. For some legacy devices the held signal is fully reset to zero at the end of the conversion period. Also, it may be useful to fully reset this capacitor as a worst-case to emulate the behavior of an input signal step. To achieve this full reset to 0 V, simply adjust Cres to a value that is larger compared to the sample and hold capacitor. For example, replacing the Cres with 55 nF makes Cres a thousand times greater than Csh (1000 × 55 pF = 55 nF). Figure 3-9 compares the output settling with Cres = 5.5 pF and 55 nF.

GUID-20211027-SS0I-L8ZT-NJXC-VR5RTSBRXLJT-low.png Figure 3-9 Output Settling With Cres = 5.5 pF and 55 nF