SBAA531 November   2021 ADS8860 , ADS8862 , ADS8881 , ADS9110 , ADS9224R

 

  1.   Trademarks
  2. 1Introduction
  3. 2 Internal Topology of SAR ADC Model
    1. 2.1  Sample and Hold
    2. 2.2  Sample and Hold Timing
    3. 2.3  Reference Transients
    4. 2.4  Bandwidth Modeling
    5. 2.5  Noise Modeling
    6. 2.6  Reference Droop and Reference Noise Errors
    7. 2.7  Gain, Offset, and Input Leakage Modeling
    8. 2.8  Differential input behavior
    9. 2.9  ESD Protection Diodes and Parasitic Capacitance
    10. 2.10 Summary of Parameters
    11. 2.11 Summary of Model Pins
  4. 3Downloading and Using PSpice® Example Projects From Web
    1. 3.1 Selecting the Amplifier and Optimizing the RC Circuit
    2. 3.2 Worst-Case Settling by Adjusting the Reset Capacitor
    3. 3.3 Verification of Reference Droop
    4. 3.4 System Noise Verification
    5. 3.5 Gain, Offset, and Input Leakage Verification
  5. 4Summary

2.7 Gain, Offset, and Input Leakage Modeling

The input voltage offset is modeled by placing a DC voltage source in series with the input. The leakage currents are modeled as DC current sources on each input. Gain error is modeled as a voltage-controlled voltage source with a gain that includes the error (GAIN = 1 + EG / 100). Figure 2-9 illustrates the gain, offset, and leakage modeling.

GUID-20211025-SS0I-FHZK-ZGN2-WVMPNF1JLP6C-low.gif Figure 2-9 Reference Noise Scaling Model