One important factor that can affect ADC conversion latency is whether settled data is the first conversion or a second or subsequent conversion. The ADS1261 conversion latency values shown in Table 2-2 are valid for the first conversion. As the ADS126x (ADS1261) Precision, 5-channel and 10-channel, 40-kSPS, 24-bit, delta-sigma ADCs with PGA and monitors data sheet states in the Conversion Latency section, second and subsequent conversion latency is equal to 1 / ODR for all filter types assuming continuous-conversion mode is used and chopping is disabled.

Figure 5-1 illustrates this concept by highlighting settled first conversions (in red) versus settled second and subsequent conversions (in green) for a sinc³ filter that experiences a multiplexer change after conversion period N completes.

Figure 5-1 First Conversion vs Second and Subsequent Conversions Using a Sinc³ Filter

In Figure 5-1, the first settled conversion result after the multiplexer change requires three conversion periods to propagate through the sinc³ filter, and occurs at the end of conversion period N+3. This is shown in red. Importantly, second and subsequent conversion results – N-5 through N for CH1 and N+4 through N+6 for CH2 – all settle in one conversion period, or 1 / ODR. This is shown in green. This result occurs because the input signal is not changing significantly during these conversion periods such that the information in each filter stage is approximately equal. Combining the data in all three filter stages therefore yields settled conversion results at the end of each conversion period. If another multiplexer change occurred after conversion period N+6 for example, the process would need to restart and first conversion latency would apply.

This behavior is documented in the ADS124S0x Low-Power, Low-Noise, Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference data sheet as well. Figure 5-2 shows how the DRDY pin responds for both the low-latency and sinc³ filter in continuous-conversion mode. Note that the term low-latency in this case is the name of a specific ADS124S08 digital filter and should not be confused with sinc filters in general, which are often considered low-latency compared to wideband filters (see Section 4).

Figure 5-2 ADS124S08 Low-Latency, Sinc³ Filter, and DRDY Pin Behavior in Continuous-Conversion Mode

The ADS124S08 low-latency filter shown in Figure 5-2 is effectively a sinc¹ filter that provides settled data in approximately one conversion period (assuming the analog input signal is settled). Comparatively, the sinc³ filter in Figure 5-2 requires three conversion periods after conversion start to provide settled data. A subsequent conversion from the sinc³ filter is available in one conversion period however. As noted in Section 2, this information is often quantified in a conversion latency table. Table 5-1 reports first conversion as well as second and subsequent conversion latency for the ADS124S08 sinc³ filter.

As noted throughout this section, first conversion latency applies after an ADC operation, as per Section 4.1. This can include manually triggering a conversion, changing certain ADC settings such as the input channel, or the initial conversion after ADC power up. Refer to the ADC data sheet for more information about any specific actions that can trigger the digital filter to reset such that first conversion latency applies.

First conversion latency does not apply when a step input occurs as per Section 4 because the ADC cannot automatically identify this condition. Instead, the user must detect this event and then manually wait the required time for settled data. Conversely, the user could manually restart the conversion process after confirming the step input has settled. The ADC then automatically waits the first-conversion latency to produce settled data, assuming the device includes this functionality.