Low-power 1-kSPS 1-ch delta-sigma ADC with PGA for seismic and energy exploration


Product details


Resolution (Bits) 24 Number of input channels 1 Sample rate (Max) (kSPS) 1 Interface type SPI Architecture Delta-Sigma Input type Differential Multi-channel configuration Rating Catalog Reference mode Ext Input range (Max) (V) 2.5 Input range (Min) (V) 0.156 Features PGA Operating temperature range (C) -40 to 85 Power consumption (Typ) (mW) 4.5 Analog voltage AVDD (Min) (V) -2.5, 0 SNR (dB) 119 Analog voltage AVDD (Max) (V) 2.5, 5 Digital supply (Min) (V) 2.25 Digital supply (Max) (V) 3.6 open-in-new Find other Precision ADCs (<=10MSPS)

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VQFN (RHF) 24 20 mm² 5 x 4 open-in-new Find other Precision ADCs (<=10MSPS)


  • Selectable Operating Modes
  • High-Resolution Mode:
    • SNR: 113 dB (1000 SPS, Gain = 1)
    • Power: 4.5 mW
  • Low-Power Mode:
    • SNR: 110 dB (1000 SPS, Gain = 1)
    • Power: 2.4 mW
  • THD: –115 dB
  • CMRR: 115 dB
  • High-Impedance CMOS PGA
    • Gains 1, 2, 4, 8, and 16
  • Data Rates: 62.5 SPS to 1000 SPS
  • Flexible Digital Filter:
    • Sinc + FIR + IIR (Selectable)
    • Linear and Minimum Phase Response
    • Programmable High-Pass Filter
  • Offset and Gain Calibration
  • Synchronization Control
  • SPI-Compatible Interface
  • Analog Power Supply: 5 V or ±2.5 V
  • Digital Power Supply: 2.5 V to 3.3 V

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The ADS1287 device is a low-power, analog-to-digital converter (ADC), with an integrated programmable gain amplifier (PGA) and finite-impulse-response (FIR) digital filter. The ADC is suitable for the demanding needs of seismic equipment requiring precision digitizing with low power consumption.

The ADC features a programmable-gain, high-impedance complementary metal oxide semiconductor (CMOS) amplifier, suitable for direct connection of geophone and hydrophone sensors to the ADC over a wide range of input signals (±2.5 V to ±0.156 V).

The ADC incorporates a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator. The modulator digital output is filtered and decimated by the internal FIR digital filter to yield the ADC conversion result.

The FIR digital filter provides data rates up to 1000 samples per second (SPS). The high-pass filter (HPF) removes DC and low frequency components from the conversion result. On-chip gain and offset scaling registers support system calibration.

Together, the amplifier, modulator, and digital filter dissipate 4.5 mW in high-resolution mode (2.4 mW in low-power mode). The ADC is packaged in a compact 5-mm × 4-mm VQFN package. The ADC is fully specified over the –40°C to +85°C temperature range.

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Technical documentation

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Type Title Date
* Datasheet ADS1287 Low-Power, 1000-SPS, Wide-Bandwidth, Analog-to-Digital Converter With Programmable Gain Amplifier datasheet (Rev. B) Aug. 27, 2019
E-book Fundamentals of Precision ADC Noise Analysis Jun. 19, 2020
Application note QFN and SON PCB Attachment (Rev. B) Aug. 24, 2018

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