4 Digital Filter Operation and Behavior

The most common types of digital filters used in delta-sigma ADCs are finite impulse response (FIR) filters such as sinc and wideband. This document focuses on the operation of sinc filters because they typically take five or fewer conversion periods to settle, resulting in low latency. Comparatively, wideband filters can initially take dozens of conversion periods to settle, making them impractical for many multiplexed applications. However, the same general timing and operation principles can be applied to an ADC with a wideband filter.

In terms of the delay from bitstream input to digital output, the simplified digital filter model introduced in the previous section is effectively a first-order sinc (sinc¹) filter. Higher-order sinc filters can be approximated as multiple sinc¹ filters in series. For example, if a sinc¹ filter has N number of delay blocks, a third-order sinc (sinc³) filter has 3 ∙ N delay blocks. Figure 4-1 shows how the digital filter model can be modified for a sinc³ filter, where each of the three stages (Sx) is comprised of N number of delay blocks.

Figure 4-1 Simplified Sinc³ Digital Filter Model

The most important result from the simplified sinc³ model in Figure 4-1 is that it takes one conversion period (1 ∙ t_CP) for the bitstream to reach the end of each stage (S1, S2, or S3), where t_CP = N ∙ t_MOD. The total delay for the bitstream to reach the end of S3 and calculate the filtered, decimated output is t_TOTAL = 3 ∙ t_CP. After this initial output is produced however, higher-order sinc filters can output filtered, decimated data after each conversion period (1 ∙ t_CP) under certain conditions (described throughout this document). This behavior is possible because the modulator sampling and digital filtering process effectively averages out transient information in the analog input. Therefore, it is typically a good assumption that the digital filter data during any X consecutive conversion periods will be similar enough to generate settled data under most conditions, where X is the sinc filter order. Operating under this assumption enables the noise reduction of a higher-order filter while avoiding the additional multi-conversion period delay required by the first output.

However, this assumption can lead to unsettled conversion results if the analog input does in fact change significantly during the conversion process. For example, Figure 4-2 illustrates how a sinc¹, a sinc³, and a fifth-order (sinc⁵) filter respond when a step input is applied to the ADC after conversion period N (t_CP(N)) completes.

Figure 4-2 Sinc Filter Response to a Step Input

In Figure 4-2, a –FS input is applied to the selected ADC channel during N-5 through N. During this time, each sinc filter outputs a settled conversion result after each conversion period. However, a +FS step input is applied to the same ADC channel between N and N+1. While this change occurs virtually instantaneously in the analog domain (assuming no analog settling time is required), settled output data is delayed leading to increased conversion latency, t_CL:

• The orange sinc¹ filter has t_CL ≅ 1 ∙ t_CP
• The blue sinc³ filter has t_CL ≅ 3 ∙ t_CP
• The purple sinc⁵ filter has t_CL ≅ 5 ∙ t_CP

Note that t_CL in the previous list is approximate because a settled conversion result can require additional processing time or user-defined delays, as per Table 2-1.

To better understand why settled data is delayed, the simplified sinc³ digital filter model from Figure 4-1 and the blue sinc³ filter response from Figure 4-2 are combined in Figure 4-3 to demonstrate how the analog input propagates through each sinc³ filter stage during conversion periods N-2 through N+3.