SBAS661C February   2015  – May 2021 ADS1262 , ADS1263

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Offset Temperature Drift Measurement
    2. 8.2 Gain Temperature Drift Measurement
    3. 8.3 Common-Mode Rejection Ratio Measurement
    4. 8.4 Power-Supply Rejection Ratio Measurement
    5. 8.5 Crosstalk Measurement (ADS1263)
    6. 8.6 Reference-Voltage Temperature-Drift Measurement
    7. 8.7 Reference-Voltage Thermal-Hysteresis Measurement
    8. 8.8 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multifunction Analog Inputs
      2. 9.3.2  Analog Input Description
        1. 9.3.2.1 ESD Diode
        2. 9.3.2.2 Input Multiplexer
      3. 9.3.3  Sensor Bias
      4. 9.3.4  Temperature Sensor
      5. 9.3.5  Power-Supply Monitor
      6. 9.3.6  PGA
      7. 9.3.7  PGA Voltage Overrange Monitors
        1. 9.3.7.1 PGA Differential Output Monitor
        2. 9.3.7.2 PGA Absolute Output-Voltage Monitor
      8. 9.3.8  ADC Reference Voltage
        1. 9.3.8.1 Internal Reference
        2. 9.3.8.2 External Reference
        3. 9.3.8.3 Power-Supply Reference
        4. 9.3.8.4 Low-Reference Monitor
      9. 9.3.9  ADC1 Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter Mode
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
        3. 9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection
      11. 9.3.11 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      12. 9.3.12 Level-Shift Voltage
      13. 9.3.13 General-Purpose Input/Output (GPIO)
      14. 9.3.14 Test DAC (TDAC)
      15. 9.3.15 ADC2 (ADS1263)
        1. 9.3.15.1 ADC2 Inputs
        2. 9.3.15.2 ADC2 PGA
        3. 9.3.15.3 ADC2 Reference
        4. 9.3.15.4 ADC2 Modulator
        5. 9.3.15.5 ADC2 Digital Filter
    4. 9.4 Device Functional Modes
      1. 9.4.1  Conversion Control
        1. 9.4.1.1 Continuous Conversion Mode
        2. 9.4.1.2 Pulse Conversion Mode
        3. 9.4.1.3 ADC2 Conversion Control (ADS1263)
      2. 9.4.2  Conversion Latency
      3. 9.4.3  Programmable Time Delay
      4. 9.4.4  Serial Interface
        1. 9.4.4.1 Chip Select (CS)
        2. 9.4.4.2 Serial Clock (SCLK)
        3. 9.4.4.3 Data Input (DIN)
        4. 9.4.4.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.4.4.5 Serial Interface Autoreset
      5. 9.4.5  Data Ready Pin (DRDY)
      6. 9.4.6  Conversion Data Software Polling
      7. 9.4.7  Read Conversion Data
        1. 9.4.7.1 Read Data Direct (ADC1 Only)
        2. 9.4.7.2 Read Data by Command
        3. 9.4.7.3 Data-Byte Sequence
          1. 9.4.7.3.1 Status Byte
          2. 9.4.7.3.2 Data Byte Format
          3. 9.4.7.3.3 Checksum Byte (CRC/CHK)
            1. 9.4.7.3.3.1 Checksum Mode (CRC[1:0] = 01h)
          4. 9.4.7.3.4 CRC Mode (CRC[1:0] = 10h)
      8. 9.4.8  ADC Clock Modes
        1. 9.4.8.1 Internal Oscillator
        2. 9.4.8.2 External Clock
        3. 9.4.8.3 Crystal Oscillator
      9. 9.4.9  Calibration
        1. 9.4.9.1 Offset and Full-Scale Calibration
          1. 9.4.9.1.1 Offset Calibration Registers
          2. 9.4.9.1.2 Full-Scale Calibration Registers
        2. 9.4.9.2 ADC1 Offset Self-Calibration (SFOCAL1)
        3. 9.4.9.3 ADC1 Offset System Calibration (SYOCAL1)
        4. 9.4.9.4 ADC2 Offset Self-Calibration ADC2 (SFOCAL2)
        5. 9.4.9.5 ADC2 Offset System Calibration ADC2 (SYOCAL2)
        6. 9.4.9.6 ADC1 Full-Scale System Calibration (SYGCAL1)
        7. 9.4.9.7 ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)
        8. 9.4.9.8 Calibration Command Procedure
        9. 9.4.9.9 User Calibration Procedure
      10. 9.4.10 Reset
        1. 9.4.10.1 Power-On Reset (POR)
        2. 9.4.10.2 RESET/PWDN Pin
        3. 9.4.10.3 Reset by Command
      11. 9.4.11 Power-Down Mode
      12. 9.4.12 Chop Mode
    5. 9.5 Programming
      1. 9.5.1 NOP Command
      2. 9.5.2 RESET Command
      3. 9.5.3 START1, STOP1, START2, STOP2 Commands
      4. 9.5.4 RDATA1, RDATA2 Commands
      5. 9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands
      6. 9.5.6 RREG Command
      7. 9.5.7 WREG Command
    6. 9.6 Register Maps
      1. 9.6.1  Device Identification Register (address = 00h) [reset = x]
      2. 9.6.2  Power Register (address = 01h) [reset = 11h]
      3. 9.6.3  Interface Register (address = 02h) [reset = 05h]
      4. 9.6.4  Mode0 Register (address = 03h) [reset = 00h]
      5. 9.6.5  Mode1 Register (address = 04h) [reset = 80h]
      6. 9.6.6  Mode2 Register (address = 05h) [reset = 04h]
      7. 9.6.7  Input Multiplexer Register (address = 06h) [reset = 01h]
      8. 9.6.8  Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]
      10. 9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]
      11. 9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 TDACP Control Register (address = 10h) [reset = 00h]
      14. 9.6.14 TDACN Control Register (address = 11h) [reset = 00h]
      15. 9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]
      16. 9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]
      17. 9.6.17 GPIO Data Register (address = 14h) [reset = 00h]
      18. 9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]
      19. 9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]
      20. 9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]
      21. 9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Isolated (or Floated) Inputs
      2. 10.1.2 Single-Ended Measurements
      3. 10.1.3 Differential Measurements
      4. 10.1.4 Input Range
      5. 10.1.5 Input Filtering
        1. 10.1.5.1 Aliasing
      6. 10.1.6 Input Overload
      7. 10.1.7 Unused Inputs and Outputs
      8. 10.1.8 Voltage Reference
      9. 10.1.9 Serial Interface Connections
    2. 10.2 Typical Application
      1. 10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ADC1 ANALOG INPUTS
Absolute input currentGain = 322nA
PGA bypassed150
Differential input currentGain = 320.1nA
PGA bypassed, VIN = 5 V150
Differential input impedancePGA enabled1GΩ
PGA bypassed40MΩ
Channel-to-channel crosstalkDC, VAVSS ≤ VINX ≤ VAVDD0.5μV/V
ADC1 PERFORMANCE
PGA gain1, 2, 4, 8, 16, 32V/V
Resolution32Bits
DRData rate2.538400SPS
Noise performanceSee Table 8-1
INLIntegral nonlinearityGain = 1 to 32, PGA bypassed312ppm
VOSOffset voltageTA = 25°CChop mode off350 / Gain800 / GainμV
Chop mode on±0.1 / Gain±0.5 / Gain
After calibration(1)Noise / 4
Offset voltage driftChop mode off30 / Gain + 10100 / Gain + 50nV/°C
Chop mode on15
GEGain errorTA = 25°C, gain = 1 to 32±50±300ppm
After calibration(1)Noise / 4
Gain driftGain = 1 to 32, and PGA bypassed0.54ppm/°C
NMRRNormal-mode rejection ratio(2)See Table 9-6
CMRRCommon-mode rejection ratio(3)fIN = 60 Hz, data rate = 20 SPS130dB
fIN = 60 Hz, data rate = 400 SPS100120
PSRRPower-supply rejection ratio(4)AVDD and AVSS8090dB
DVDD80120
ADC2 ANALOG INPUTS (ADS1263)
Absolute input currentGain = 162nA
Differential input currentGain = 160.5nA
ADC2 PERFORMANCE (ADS1263)
Gain1, 2, 4, 8, 16, 32, 64, 128V/V
Resolution24Bits
DRData rate10, 100, 400, 800SPS
Noise performanceSee Table 8-3
INLIntegral nonlinearityGain = 1 to 64420ppm
Gain = 128730
VOSOffset voltageTA = 25°C, gain = 1 to 128±150±500μV
Offset voltage driftGain = 1 to 12830200nV/°C
GEGain errorTA = 25°C, gain = 1 to 128±500±3000ppm
Gain driftGain = 1 to 12815ppm/°C
NMRRNormal-mode rejection ratioSee Table 9-11
CMRRCommon-mode rejection ratiofIN = 60 Hz, DR = 10 SPS110dB
fIN = 60 Hz, DR = 400 SPS, gain = 87590
PSRRPower-supply rejection ratioAVDD and AVSS7590dB
CROSSTALK
CrosstalkADC1 to ADC220μV/V
ADC2 to ADC11
EXTERNAL VOLTAGE REFERENCE INPUTS
Reference input current(5)ADC1150nA
ADC21
Input current vs voltageVREF = 2 V to 4.8 V, ADC110nA/V
Input current driftADC10.1nA/°C
Input impedanceDifferential, ADC150MΩ
Low reference monitorThreshold, ADC10.40.6V
INTERNAL VOLTAGE REFERENCE
Reference voltage2.5V
Initial accuracyTA = 25°C±0.1%±0.2%
Reference voltage temperature driftTA = 0°C to +85°C26ppm/°C
TA = –40°C to +105°C412
Reference voltage long term driftTA = 85°C, 1st 1000 hr50ppm
Thermal hysteresisFirst 0°C to 85°C cycle50ppm
Output current-1010mA
Load regulation40μV/mA
Start-up timeSettling time to ±0.001% final value50ms
TEMPERATURE SENSOR
VoltageTA = 25°C122.4mV
Temperature coefficient420μV/°C
CURRENT SOURCES (IDAC1, IDAC2)
Currents50, 100, 250, 500, 750,
1000, 1500, 2000, 2500, 3000		μA
Compliance rangeAll currentsVAVSSVAVDD – 1.1V
Absolute errorAll currents±0.7%±4%
Match errorIDAC1 current = IDAC2 current±0.1%±1%
IDAC1 current ≠ IDAC2 current±1%
Temperature driftAbsolute50ppm/°C
Match520
LEVEL-SHIFT VOLTAGE
Voltage(VAVDD + VAVSS) / 2V
Output impedance100Ω
SENSOR BIAS
Currents±0.5, ±2, ±10, ±50, ±200μA
Pull-up/pull-down resistor10MΩ
TEST DAC (TDAC)
DAC reference voltageVAVDD – VAVSSV
Differential output voltage18 binary weighted settings–44V
Absolute output voltageTo VAVSS0.54.5V
Accuracy±0.1%±1.5%
Output impedanceSee Table 9-8
PGA OVER-RANGE MONITOR
Differential alarmThreshold±105%FSR
Differential alarm accuracy±1%±3%
Absolute alarm thresholdsLow thresholdVAVSS + 0.2V
High thresholdVAVDD – 0.2V
ADC CLOCK
fCLKInternal oscillator frequency7.3728MHz
Internal oscillator accuracy±0.5%±2%
External crystal start-up timeSee Table 9-21 for recommended crystals20ms
GENERAL-PURPOSE INPUT/OUTPUTS (GPIO)(6)
VOHHigh-level output voltageIOH = 1 mA0.8 · VAVDDV
VOLLow-level output voltageIOL = –1 mA0.2 · VAVDDV
VIHHigh-level input voltage0.7 · VAVDDVAVDDV
VILLow-level input voltageVAVSS0.3 · VAVDDV
Input hysteresis0.5V
DIGITAL INPUT/OUTPUT (Other Than GPIO)
VOHHigh-level output voltageIOH = 1 mA0.8 · VDVDDV
IOH = 8 mA0.75 · VDVDD
VOLLow-level output voltageIOL = –1 mA0.2 · VDVDDV
IOL = –8 mA0.2 · VDVDD
VIHHigh-level input voltage0.7 · VDVDDVDVDDV
VILLow-level input voltageVDGND0.3 · VDVDDV
Input hysteresis0.1V
Input leakage±10μA
POWER SUPPLY
IAVDD
IAVSS		Analog supply currentActive mode, voltage reference offADS12624mA
Active mode, voltage reference onADS12624.26.5
Active mode, voltage reference onADS12634.36.5
Power-down mode215μA
IDVDDDigital supply currentActive modeADS1262 ADS126311.25mA
Power-down mode(7)2550μA
PDPower dissipationActive mode, voltage reference onADS12622437mW
Active mode, voltage reference onADS12632537
Power-down mode90240μW
(1) Offset and gain calibration accuracy on the order of ADC conversion noise / 4. Conversion noise depends on data rate and PGA gain.
(2) Normal-mode rejection ratio depends on the digital filter setting.
(3) Common-mode rejection ratio is specified at date rate 20 SPS and 400 SPS.
(4) Power-supply rejection ratio is specified at dc.
(5) Specified with VAVSS ≤ VREFN and VREFP ≤ VAVDD. For reference input voltage exceeding VAVDD or VAVSS, the ADC1 reference input current = 10 nA/ mV.
(6) GPIO input and output voltages are referenced to VAVSS.
(7) External CLK input stopped. All other digital inputs maintained at VDVDD or VDGND.