SBASAO4B December   2024  – June 2025 ADC3568 , ADC3569

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3568 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3569 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3568
    11. 6.11 Typical Characteristics, ADC3569
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS (SDR) - Default
        2. 8.3.9.2 Parallel LVDS (DDR)
        3. 8.3.9.3 SLVDS with Decimation
          1. 8.3.9.3.1 SLVDS - Status Bit Insertion
        4. 8.3.9.4 Output Data Format
        5. 8.3.9.5 32-bit Output Resolution
        6. 8.3.9.6 Output Scrambler
        7. 8.3.9.7 Output MUX
        8. 8.3.9.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.5 Overrange

The device triggers the overrange indicator when the signal crosses the representable digital range. The overrange output can be configured in registers 0x10A/0x10B. The latency of the OVR indication is equal or less than the data latency.

The OVR can be indicated in two different ways:

  • GPIO pin: can be configured using register 0x146
  • LSB data: the OVR signal replaces the LSB of the output data (register 0x116). In decimation mode the OVR signal replaces the LSB in every DDC output stream.