SBASAO4B December   2024  – June 2025 ADC3568 , ADC3569

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3568 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3569 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3568
    11. 6.11 Typical Characteristics, ADC3569
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS (SDR) - Default
        2. 8.3.9.2 Parallel LVDS (DDR)
        3. 8.3.9.3 SLVDS with Decimation
          1. 8.3.9.3.1 SLVDS - Status Bit Insertion
        4. 8.3.9.4 Output Data Format
        5. 8.3.9.5 32-bit Output Resolution
        6. 8.3.9.6 Output Scrambler
        7. 8.3.9.7 Output MUX
        8. 8.3.9.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.8.4 Numerically Controlled Oscillator (NCO)

Each digital down-converter (DDC) uses a 48-bit numerically controlled oscillator (NCO) to fine tune the frequency placement prior to the digital filtering. Up to four different NCO frequencies for each DDC are programmed using SPI register writes. The digital NCOs are designed to have a SFDR of at least 100dB.

ADC3568 ADC3569 NCO Block Diagram Figure 8-54 NCO Block Diagram

There are two different NCO operating modes - phase continuous and infinite phase coherent.

  1. Phase Continuous NCO :During a NCO frequency change, the NCO phase gradually adjusts to the new frequency as shown in Figure 8-55 (left). The 'dashed' line shows the phase of original f1 frequency.
  2. Infinite Phase Coherent NCO: With a phase coherent NCO, all frequencies are synchronized to a single event using SYSREF. This enables an infinite amount of frequency hops without the need to reset the NCO as phase coherency is maintained between frequency hops. This is illustrated in Figure 8-55 (right). When returning to the original frequency f1 the NCO phase appears as if the NCO had never changed frequencies.

ADC3568 ADC3569 Phase Continuous (left) and Infinite Phase Coherent (right) NCO Frequency SwitchingFigure 8-55 Phase Continuous (left) and Infinite Phase Coherent (right) NCO Frequency Switching

The oscillator generates a complex exponential sequence of:

Equation 1. ejωn (default) or e–jωn

where: frequency (ω) is specified as a signed number by the 48-bit register setting

The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a frequency equal to fIN + fNCO. The NCO frequency can be tuned from –FS/2 to +FS/2 and is processed as a signed, 2s complement number.

The NCO frequency setting is set by the 48-bit register value given and calculated as:

Equation 2. NCO frequency (0 to + FS/2): NCO = fNCO × 248 / FS
Equation 3. NCO frequency (-FS/2 to 0): NCO = (fNCO + FS) × 248 / FS

where:

  • NCO = NCO register setting (decimal value)
  • fNCO = Desired NCO frequency (MHz)
  • FS = ADC sampling rate (MSPS)

The NCO programming is illustrated with this example:

  • ADC sampling rate FS = 500MSPS
  • Desired NCO frequency = 120MHz

Equation 4. NCO frequency setting = fNCO × 248 / FS = 120MHz x 248 / 500 MSPS = 67,553,994,410,557

Table 8-9 shows the register writes to set frequency 0 of the NCO of DDC0 to that frequency:

Table 8-9 Example register writes to change NCO frequency
ADDRDATADESCRIPTION
0x2000x3D

Set the NCO0 frequency to 120MHz (67,553,994,410,557)

which is 0x3D70 A3D7 0A3D starting LSB in 0x200.

0x2010x0A
0x2020xD7
0x2030xA3
0x2040x70
0x2050x3D
0x1650x00Load and update all NCOs with the new frequencies.
0x1650x01
0x1650x00
0x1600x00Issue a manual SYSREF (via pin or SPI SYSREF) to update the NCO frequencies.
0x1600x04
0x1600x00