SBASAO4B December   2024  – June 2025 ADC3568 , ADC3569

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3568 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3569 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3568
    11. 6.11 Typical Characteristics, ADC3569
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS (SDR) - Default
        2. 8.3.9.2 Parallel LVDS (DDR)
        3. 8.3.9.3 SLVDS with Decimation
          1. 8.3.9.3.1 SLVDS - Status Bit Insertion
        4. 8.3.9.4 Output Data Format
        5. 8.3.9.5 32-bit Output Resolution
        6. 8.3.9.6 Output Scrambler
        7. 8.3.9.7 Output MUX
        8. 8.3.9.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RTD Package, 64 Pin VQFNP
(Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
AGND16, 33IAnalog ground, 0V
AINM19IChannel A differential signal input, negative connection. The differential input has programmable internal termination (100Ω or 200Ω) and is self biased.
AINP18IChannel A differential signal input, positive connection.
AVDD1215, 22, 34IAnalog 1.2V supply
AVDD1817, 20, 29, 32IAnalog 1.8V supply
CLKGND23, 26IClock ground, 0V
CLKP24IDevice sampling clock differential input. AC coupling and terminating the clock signal externally for best AC performance is recommended. The differential input is self biased to the input common-mode voltage (0.75V).
CLKM25I
DCLKP55ODifferential LVDS data bit clock output.
DCLKM56O
DGND1, 48, 57IDigital ground, 0V
DOUT0/FCLKM37ODifferential LVDS data bit output lane 0. In decimation mode this pin turns to the differential SLVDS frame clock output, replacing the LSB.
DOUT0/FCLKP38O
DOUT1M39ODifferential LVDS data bit output lane 1. Can be left floating and powered down via SPI if not used.
DOUT1P40O
DOUT2M41ODifferential LVDS data bit output lane 2. Can be left floating and powered down via SPI if not used.
DOUT2P42O
DOUT3M43ODifferential LVDS data bit output lane 3. Can be left floating and powered down via SPI if not used.
DOUT3P44O
DOUT4M45ODifferential LVDS data bit output lane 4. Can be left floating and powered down via SPI if not used.
DOUT4P46O
DOUT5P49ODifferential LVDS data bit output lane 5. Can be left floating and powered down via SPI if not used.
DOUT5M50O
DOUT6P51ODifferential LVDS data bit output lane 6. Can be left floating and powered down via SPI if not used.
DOUT6M52O
DOUT7P53ODifferential LVDS data bit output lane 7. Can be left floating and powered down via SPI if not used.
DOUT7M54O
DOUT8M59ODifferential LVDS data bit output lane 8. Can be left floating and powered down via SPI if not used.
DOUT8P60O
DOUT9M61ODifferential LVDS data bit output lane 9. Can be left floating and powered down via SPI if not used.
DOUT9P62O
DOUT10M63ODifferential LVDS data bit output lane 10. Can be left floating and powered down via SPI if not used.
DOUT10P64O
DOUT11P3ODifferential LVDS data bit output lane 11. Can be left floating and powered down via SPI if not used.
DOUT11M4O
DOUT12P5ODifferential LVDS data bit output lane 12. Can be left floating and powered down via SPI if not used.
DOUT12M6O
DOUT13P7ODifferential LVDS data bit output lane 13. Can be left floating and powered down via SPI if not used.
DOUT13M8O
DOUT14P9ODifferential LVDS data bit output lane 14. Can be left floating and powered down via SPI if not used.
DOUT14M10O
DOUT15P11ODifferential LVDS data bit output lane 15. Can be left floating and powered down via SPI if not used.
DOUT15M12O
DVDD122, 47IDigital 1.2V supply
DVDD1858IDigital 1.8V supply
GPIO027I/OSynchronization or control input or status output. Can be left floating if not used.
GPIO128I/OControl input or status output or external voltage reference (1.2V). Can be left floating if not used.
NC 30,31 - Do not connect
RESET35IHardware reset. Active high. This pin has an internal 21kΩ pull-down resistor to DGND.
SCLK13ISerial interface clock for the serial interface programming. This pin has an internal 21kΩ pull-up resistor to DVDD18.
SDIO36I/OSerial interface data input/output. This pin has an internal 21kΩ pull-up resistor to DVDD18.
SEN14ISerial interface chip select. This pin has an internal 21kΩ pull-up resistor to DVDD18.
VCM21OCommon mode voltage output (1.4V)
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.