SBASAO4B December   2024  – June 2025 ADC3568 , ADC3569

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3568 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3569 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3568
    11. 6.11 Typical Characteristics, ADC3569
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS (SDR) - Default
        2. 8.3.9.2 Parallel LVDS (DDR)
        3. 8.3.9.3 SLVDS with Decimation
          1. 8.3.9.3.1 SLVDS - Status Bit Insertion
        4. 8.3.9.4 Output Data Format
        5. 8.3.9.5 32-bit Output Resolution
        6. 8.3.9.6 Output Scrambler
        7. 8.3.9.7 Output MUX
        8. 8.3.9.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.8.3 Decimation Filter Configuration

The operation of the digital decimation filter can be controlled using registers 0x163 to 0x169. The NCO frequencies are mapped to registers 0x200..0x2DF. The DDC is versatile and can support many operating modes.

Table 8-7 Configuration of the DDC
ADDR DESCRIPTION
0x163 Connect ADC ChA to desired DDC. By default the ADC is connected to two DDCs.
0x164 Select NCO mode and update NCO frequencies
0x165 Configure NCO frequency update
0x166 Assign NCO frequency 0..3 to each NCO
0x167/168 Select Decimation for each DDC if unequal decimation factors are used
0x169 Configure # of DDCs and common decimation factor

The following sequence can be used to configure the DDC for a static operating mode (either fixed NCO/slow changing NCO frequencies): Complex decimation /1024, quad band 32-bit output

Table 8-8 DDC Example Configuration
ADDR DATA DESCRIPTION
0x162 0x06 Select complex decimation, 32-bit output resolution.
0x169 0x1A Configuration to 4x DDC (quad band) with common decimation of 1024.