SBASAP7 Data sheet

SBASAP7A December 2024 – April 2025 ADC3664-SP

PRODUCTION DATA

7.5.4.1 Detailed Register Description

Figure 7-37 Register 0x00

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	RESET
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-9 Register 0x00 Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	R/W	0	Must write 0.
0	RESET	R/W	0	This bit resets all internal registers to the default values and self clears to 0.

Figure 7-38 Register 0x07

7	6	5	4	3	2	1	0
IF_MAPPER_SEL			0	IF_SEL_EN	IF_MODE_SEL
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-10 Register 0x07 Field Descriptions

Bit	Field	Type	Reset	Description
7-5	IF_MAPPER_SEL	R/W	000	Select the proper bit mapping based on the desired interface mode. The bit mapping for each mode is described under Section 7.3.4.5. The default bit mapping for each interface mode is loaded from internal fuses and also requires a fuse load sequence (see Table 7-15). It is imperative that this field is set before the fuse load sequence. 001: bit mapping for 2-wire, 18-bit and 14-bit. 010: bit mapping for 2-wire, 16-bit. 011: bit mapping for 1-wire. 100: bit mapping for 1/2-wire.
4	0	R/W	0	Must write 0.
3	IF_SEL_EN	R/W	0	Enables selection of the output interface mode.0: interface mode selection is disabled. 1: interface mode selection is enabled.
2-0	IF_MODE_SEL	R/W	000	Select the desired output interface mode (2-wire, 1-wire, or 1/2-wire). IF_SEL_EN must be set to 1 for this setting to take effect.011: interface mode set to 2-wire. 100: interface mode set to 1-wire. 101: interface mode set to 1/2-wire.

Figure 7-39 Register 0x08

7	6	5	4	3	2	1	0
0	0	0	0	0	PDN_A	PDN_B	PDN_ GLOBAL
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-11 Register 0x08 Field Descriptions

Bit	Field	Type	Description
7-3	0	R/W	Must write 0.
2	PDN_A	R/W	Power down ADC A.0: ADC A is enabled. 1: ADC A is powered down.
1	PDN_B	R/W	Power down ADC B.0: ADC B is enabled. 1: ADC B is powered down.
0	PDN_GLOBAL	R/W	Device global power down.0: device is enabled. 1: device is powered down.

Figure 7-40 Register 0x09

7	6	5	4	3	2	1	0
0	0	0	0	PDN_DA1	PDN_DA0	PDN_DB1	PDN_DB0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-12 Register 0x09 Field Descriptions

Bit	Field	Type	Description
7-4	0	R/W	Must write 0.
3	PDN_DA1	R/W	Lane A1 power down control. This lane is not powered down automatically in the 1-wire and 1/2-wire interface modes.0: lane A1 is enabled. 1: lane A1 is powered down.
2	PDN_DA0	R/W	Lane A0 power down control.0: lane A0 is enabled. 1: lane A0 is powered down.
1	PDN_DB1	R/W	Lane B1 power down control. This lane is not powered down automatically in the 1-wire and 1/2-wire interface modes.0: lane B1 is enabled. 1: lane B1 is powered down.
0	PDN_DB0	R/W	Lane B0 power down control. This lane is not powered down automatically in the 1/2-wire interface mode.0: lane B0 is enabled. 1: lane B0 is powered down.

Figure 7-41 Register 0x0E

7	6	5	4	3	2	1	0
SYNC_ PIN_EN	SPI_SYNC_ VAL	SYNC_SRC_ SEL	0	CTRL_MODE	REF_SEL		SE_CLK_EN
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-13 Register 0x0E Field Descriptions

Bit	Field	Type	Reset	Description
7	SYNC_PIN_EN	R/W	0	The PDN/SYNC pin is a dual purpose pin. 0: the PDN/SYNC pin is configured as the global power down control pin. 1: the PDN/SYNC pin is configured as a SYNC pin.
6	SPI_SYNC_VAL	R/W	0	Set the internal SYNC state when SYNC_SRC_SEL is set. SPI_SYNC_VAL should be toggled to issue a SYNC sequence. Doesn't automatically reset to 0.0: internal SYNC state is set to 0 (normal operation). 1: internal SYNC state set to 1 (initiate SYNC sequence).
5	SYNC_SRC_SEL	R/W	0	Select the SYNC source for the device.0: SYNC internal state from the PDN/SYNC pin. 1: SYNC internal state from the SPI_SYNC_VAL field.
4	0	R/W	0	Must write 0.
3	CTRL_MODE	R/W	0	Select if the ADC reference mode and sample clock type is set through the CTRL pin or based on the REF_SEL and SE_CLK_EN fields.0: the CTRL pin controls the ADC reference mode and sample clock input type. 1: the REF_SEL and SE_CLK_EN fields control the ADC reference mode and sampling clock type, respectively.
2-1	REF_SEL	R/W	00	Select the ADC reference mode via SPI. CTRL_MODE must be set to 1 for this setting to take effect.00: internal 1.6V reference used as the ADC reference. 10: the ADC reference is provided externally.
0	SE_CLK_EN	R/W	0	Select the ADC sampling clock input type. CTRL_MODE must be set to 1 for this setting to take effect.0: the ADC sampling clock input configured as a differential input. 1: the ADC sampling clock input configured as a single-ended input.

Figure 7-42 Register 0x11

7	6	5	4	3	2	1	0
0	0	0	0	0	DLL_PDN	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-14 Register 0x11 Field Descriptions

Bit	Field	Type	Description
7-3	0	R/W	Must write 0.
2	DLL_PDN	R/W	Select power down state for an internal DLL. See Section 7.3.2.2.
1-0	0	R/W	Must write 0.

Figure 7-43 Register 0x13

7	6	5	4	3	2	1	0
0	0	0	0	0	0		FUSE_LD
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-15 Register 0x13 Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	R/W	0	Must write 0.
0	FUSE_LD	R/W	0	Internal fuse load control. Set to 1, wait for ~1ms, and set to 0 to load the device configuration based on the interface mode settings.

Figure 7-44 Register 0x14/15/16

7	6	5	4	3	2	1	0
PAT_DATA[7:0]
PAT_DATA[15:8]
TP1_MODE			TP0_MODE			PAT_DATA[17:16]
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-16 Register 0x14/15/16 Field Descriptions

Bit	Field	Type	Reset	Description
7-5	TP1_MODE	R/W	000	Located in 0x16. Select the mode for test pattern 1 (default data path for ADC B). 000: test pattern is disabled (normal output mode). 010: ramp pattern mode where PAT_DATA sets the ramp pattern increment size. 011: constant pattern mode where PAT_DATA[17:0] is the MSB aligned constant pattern.
4-2	TP0_MODE	R/W	000	Located in 0x16. Select the mode for test pattern 0 (default data path for ADC A). 000: test pattern is disabled (normal output mode). 010: ramp pattern mode where PAT_DATA sets the ramp pattern increment size. 011: constant pattern mode where PAT_DATA[17:0] is the MSB aligned constant pattern.
1-0, 7-0, 7-0	PAT_DATA[17:0]	R/W	0	PAT_DATA[17:0] is split across three registers: [17:16] in 0x16, [15:8] in 0x15, and [7:0] in 0x14. The PAT_DATA: Used as the constant pattern when the test pattern mode is set to constant pattern. Used as the ramp pattern step size when test pattern mode is set to ramp pattern.

Figure 7-45 Register 0x19

7	6	5	4	3	2	1	0
FCLK_SRC	0	0	FCLK_DIV	0	0	0	TOG_FCLK
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-17 Register 0x19 Field Descriptions

Bit	Field	Type	Description
7	FCLK_SRC	R/W	Select the FCLK signal source. See Table 7-18.
6-5	0	R/W	Must write 0.
4	FCLK_DIV	R/W	Select the FCLK divider setting. See Table 7-18.
3-1	0	R/W	Must write 0.
0	TOG_FCLK	R/W	Select the FCLK toggle setting. See Table 7-18.

Table 7-18 FCLK Settings Based on Device Mode

Mode	Interface Mode	FCLK_SRC	FCLK_DIV	TOG_FCLK
DSP Features Disabled/Real Decimation	2-wire	0	1	0
	1-wire	0	0	0
	1/2-wire	0	0	0
Complex Decimation	2-wire	1	0	0
	1-wire	1	0	0
	1/2-wire	0	0	1

Figure 7-46 Register 0x1A

7	6	5	4	3	2	1	0
0	HALF_ SWING_EN	0	0	0	0	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-19 Register 0x1A Field Descriptions

Bit	Field	Type	Description
7	0	R/W	Must write 0.
6	HALF_SWING_EN	R/W	This bit reduces the LVDS output swing.
5-0	0	R/W	Must write 0.

Figure 7-47 Register 0x1B

7	6	5	4	3	2	1	0
RES_SEL_EN	20B_EN	RES_SEL			0	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-20 Register 0x1B Field Descriptions

Bit	Field	Type	Reset	Description
7	RES_SEL_EN	R/W	0	Select if the resolution select block is enabled. The resolution select block is not needed for setting the output resolution to 20-bit. 0: the resolution select block is disabled. 1: the resolution select block is enabled.
6	20B_EN	R/W	0	Control 20-bit output resolution mode.0: 20-bit output resolution mode is disabled. 1: 20-bit output resolution mode is enabled.
5-3	RES_SEL	R/W	010	Select the output resolution. If the DSP features are disabled, RES_SEL_EN needs to be set to 1 for this setting to take effect.000: the output resolution is set to 18-bit. 001: the output resolution is set to 16-bit. 010: the output resolution is set to 14-bit.
2-0	0	R/W	0	Must write 0.

Table 7-21 Setting Output Resolution Based on Mode

Mode	RES_SEL_EN	RES_SEL
DSP Features Disabled	1	000: the output resolution is set to 18-bit. 001: the output resolution is set to 16-bit. 010: the output resolution is set to 14-bit.
Real Decimation	0
Complex Decimation	0

Figure 7-48 Register 0x1E

7	6	5	4	3	2	1	0
0	0	0	0	LVDS_DATA_DEL		LVDS_DCLK_DEL
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-22 Register 0x1E Field Descriptions

Bit	Field	Type	Reset	Description
7-4	0	R/W	0	Must write 0
3-2	LVDS_DATA_DEL	R/W	00	Control delay on the data lanes.00: no delay (normal mode). 01: the data lanes are advanced by 50ps. 10: the data lanes are delayed by 50ps. 11: the data lanes are delayed by a 100ps.
1-0	LVDS_DCLK_DEL	R/W	00	Control delay on the interface data clock.00: no delay (normal mode). 01: DCLK is advanced by 50ps. 10: DCLK is delayed by 50ps. 11: DCLK is delayed by a 100ps.

Figure 7-49 Register 0x20/21/22

7	6	5	4	3	2	1	0
FCLK_PAT[7:0]
FCLK_PAT_[15:8]
0	SCR_EN	0	0	FCLK_PAT_[19:16]
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-23 Register 0x20/21/22 Field Descriptions

Bit	Field	Type	Reset	Description
6	SCR_EN	R/W	0	Located in 0x22. Configure the scrambler enable state. Scrambler should only be used in the 2-wire interface mode. DSP_EN needs to be set to 1 for this setting to take effect. 0: the output scrambler is disabled. 1: the output scrambler is enabled.
3-0, 7-0, 7-0	FCLK_PAT[19:0]	R/W	0xFFC00	FCLK_PAT is split across three registers. [19:16] in 0x22, [15:8] in 0x21, and [7:0] in 0x20. See Table 7-24.

Table 7-24 FCLK Pattern in Different Modes

Mode	Output Resolution	2-wire	1-wire	1/2-wire
DSP Features Disabled/Real Decimation	14-bit	0xFFC00	0xFE000	0xFFC00
	16-bit		0xFF000
	18-bit		0xFF800
	20-bit		0xFFC00
Complex Decimation	14-bit		0xFFFFF	0xFFFFF
	16-bit
	18-bit
	20-bit

Figure 7-50 Register 0x24

7	6	5	4	3	2	1	0
0	0	AVG_EN	DDC_INP_SEL		DSP_EN	DDC_EN	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-25 Register 0x24 Field Descriptions

Bit	Field	Type	Description
7-6	0	R/W	Must write 0.
5	AVG_EN	R/W	Control the averaging block which averages the outputs of ADCs A & B.0: the averaging block is disabled. 1: the averaging block is enabled.
4-3	DDC_INP_SEL	R/W	Select the source of the DDC input. DDC_MUX_EN must be set to 1 for this setting to take effect.00: output of ADC A as DDC0 input. Output of ADC B as DDC1 input. 01: output of ADC A as DDC0 and DDC1 input. 10: output of ADC B as DDC0 and DDC1 input. 11: output of ADC averaging block as DDC0 and DDC1 input.
2	DSP_EN	R/W	Enable the DSP features data path. 0: DSP features data path is disabled. 1: DSP features data path is enabled.
1	DDC_EN	R/W	Enable the DDCs.0: DDCs are disabled. 1: DDCs are enabled.
0	0	R/W	Must write 0.

Figure 7-51 Register 0x25

7	6	5	4	3	2	1	0
DDC_MUX_EN	DEC_FACTOR			DDC_MODE	0	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-26 Register 0x25 Field Descriptions

Bit	Field	Type	Reset	Description
7	DDC_MUX_EN	R/W	0	Control the DDC_MUX enable. The DDC_MUX must be enabled for DDC_INP_SEL to take effect.0: the DDC_MUX is disabled. 1: the DDC_MUX enabled,
6-4	DEC_FACTOR	R/W	000	Decimation factor setting. 000: no decimation. 001: decimation by 2. 010: decimation by 4. 011: decimation by 8. 100: decimation by 16. 101: decimation by 32.
3	DDC_MODE	R/W	0	DDC mode and applies to both DDCs.0: the DDC mode is set to complex decimation. 1: the DDC mode is set to real decimation.
2-1	0	R/W	0	Must write 0.

Figure 7-52 Register 0x26

7	6	5	4	3	2	1	0
DDC0_GAIN		NCO0_RES	0	DDC1_GAIN		NCO1_RES	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-27 Register 0x26 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DDC0_GAIN	R/W	00	Select the digital gain setting for DDC0 to compensate for the complex decimation amplitude reduction for DDC0. 00: no digital gain added. 10: 6-dB digital gain is added (useful in the complex decimation mode only).
5	NCO0_RES	R/W	0	Toggling this bit resets the NCO phase of NCO0 in DDC0 and loads the current FCW0 as the NCO frequency. This setting is not self clearing.
4	0	R/W	0	Must write 0.
3-2	DDC0_GAIN	R/W	00	Select the digital gain setting for DDC1 to compensate for the complex decimation amplitude reduction for DDC1. 00: no digital gain added. 10: 6-dB digital gain is added (useful in the complex decimation mode only).
1	NCO1_RES	R/W	0	Toggling this bit resets the NCO phase of NCO1 in DDC1 and loads the current FCW1 as the NCO frequency. This setting is not self clearing.
0	0	R/W	0	Must write 0.

Figure 7-53 Register 0x27

7	6	5	4	3	2	1	0
0	0	0	IQ0_ORDER	Q0_DEL	0	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-28 Register 0x27 Field Descriptions

Bit	Field	Type	Description
7-5	0	R/W	Must write 0.
4	IQ0_ORDER	R/W	Swaps the I and Q output order for DDC0. Set to 0 if not using complex decimation; otherwise, see Table 7-29.
3	Q0_DEL	R/W	This delays the quadrature output of DDC0 by one sample. Set to 0 if not using complex decimation; otherwise, see Table 7-29.
2-0	0	R/W	Must write 0

Table 7-29 IQ_ORDER and Q_DEL Register Settings for Complex Decimation

Interface Mode	IQ_ORDER	Q_DEL
2-wire	1	0
1-wire	0	1
1/2-wire	1	1

Figure 7-54 Register 0x2A/B/C/D

7	6	5	4	3	2	1	0
FCW0[7:0]
FCW0[15:8]
FCW0[23:16]
FCW0[31:24]
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-30 Register 0x2A/2B/2C/2D Field Descriptions

Bit	Field	Type	Reset	Description
	FCW0[31:0]	R/W	0	FCW for NCO0 and is split across four registers. [31:24] in 0x2D, [23:16] in 0x2C, [15:8] in 0x2B, and [7:0] in 0x2A.

Figure 7-55 Register 0x2E

7	6	5	4	3	2	1	0
0	0	0	IQ1_ORDER	Q1_DEL	0	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-31 Register 0x2E Field Descriptions

Bit	Field	Type	Description
7-5	0	R/W	Must write 0
4	IQ1_ORDER	R/W	Swaps the I and Q output order for DDC1. Set to 0 if not using complex decimation; otherwise, see Table 7-29.
3	Q1_DEL	R/W	This delays the quadrature output of DDC1 by one sample. Set to 0 if not using complex decimation; otherwise, see Table 7-29.
2-0	0	R/W	Must write 0.

Figure 7-56 Register 0x31/32/33/34

7	6	5	4	3	2	1	0
FCW1[7:0]
FCW1[15:8]
FCW1[23:16]
FCW1[31:24]
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-32 Register 0x31/32/33/34 Field Descriptions

Bit	Field	Type	Reset	Description
	FCW1[31:0]	R/W	0	FCW for NCO1 and is split across four registers. [31:24] in 0x34, [23:16] in 0x33, [15:8] in 0x32, and [7:0] in 0x31.

Figure 7-57 Register 0x39..0x60

7	6	5	4	3	2	1	0
BIT_MAPPER_A
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-33 Register 0x39..0x60 Field Descriptions

Bit	Field	Type	Reset	Description
	BIT_MAPPER_A	R/W	0	See the Section 7.3.4.5.

Figure 7-58 Register 0x61..0x88

7	6	5	4	3	2	1	0
BIT_MAPPER_B
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-34 Register 0x61..0x88 Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BIT_MAPPER_B	R/W	0	See the Section 7.3.4.5.

Figure 7-59 Register 0x8F

7	6	5	4	3	2	1	0
0	0	0	0	0	0	FORMAT_A	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-35 Register 0x8F Field Descriptions

Bit	Field	Type	Description
7-2	0	R/W	Must write 0
1	FORMAT_A	R/W	Sets the output data format for the channel A data path. The DSP_EN must be set to 1 for this setting to take effect.0: output data format is 2s complement. 1: output data format is offset binary.
0	0	R/W	Must write 0

Figure 7-60 Register 0x92

7	6	5	4	3	2	1	0
0	0	0	0	0	0	FORMAT_B	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-36 Register 0x92 Field Descriptions

Bit	Field	Type	Description
7-2	0	R/W	Must write 0
1	FORMAT_B	R/W	Sets the output data format for the channel B data path. The DSP_EN must be set to 1 for this setting to take effect.0: output data format is 2s complement. 1: output data format is offset binary.
0	0	R/W	Must write 0

Table 7-37 Register 0x244

7	6	5	4	3	2	1	0
0	0	DCLKIN_VCM	0	0	0	0	0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 7-38 Register 0x244 Field Descriptions

Bit	Field	Type	Description
7-6	0	R/W	Must write 0.
5	DCLKIN_VCM	R/W	This bit sets the common-mode source for DCLKIN. 0: DCLKIN common-mode is provided externally. 1: DCLKIN is internally biased to a 1.2V common-mode.
4-0	0	R/W	Must write 0.