SBASAX3B May   2025  – April 2026 ADS9326 , ADS9327

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics 
    6. 6.6  Electrical Characteristics: AVDD = 5V
    7. 6.7  Electrical Characteristics: AVDD = 3.3V
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Reference
        1. 7.3.2.1 Internal Reference
          1. 7.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 7.3.2.2 External Reference
        3. 7.3.2.3 External Reference With External Reference Buffer
      3. 7.3.3 Burst Sample Operation
      4. 7.3.4 ADC Transfer Function
      5. 7.3.5 Programmable Data Averaging Filter
        1. 7.3.5.1 Simple Average
          1. 7.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 7.3.5.2 Moving Average
      6. 7.3.6 Channel Averaging
      7. 7.3.7 Common-Mode Voltage Output
      8. 7.3.8 CRC on Output Data Interface
      9. 7.3.9 ADC Output Data Randomizer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Low-Latency Mode
      4. 7.4.4 CS-CONVST Short Mode
      5. 7.4.5 Register Read Mode
      6. 7.4.6 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1  Data Interface
      2. 7.5.2  Data Frame Width
      3. 7.5.3  SPI Modes
      4. 7.5.4  CONVST Inversion
      5. 7.5.5  SCLK Echo Mode
      6. 7.5.6  Daisy-Chain Mode
      7. 7.5.7  SPI Frame Length for Register Operations
      8. 7.5.8  Register Map Lock
      9. 7.5.9  Register Write
      10. 7.5.10 Register Read
  9. 8 Register Map
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.5.1 Simple Average

To enable simple data averaging, write 1b to SAVG_EN in address 0x0D and select the window size by writing to SAVG_MODE in address 0x0D.

Table 7-7 specifies the improvement in SNR with simple data averaging and the corresponding impact on ADC output rate. Figure 7-12 illustrates the ADC output timing for a simple average of four samples. When averaging is enabled, the output data frame width increases by four bits, as described in the Data Frame Width section.

Table 7-5 Simple Average - ADC Output Data Rate and SNR vs Data Averaging
OVERSAMPLING RATIO SNR - ADS9327 (16-BIT) MAXIMUM OUTPUT DATA RATE
No averaging 93.2dB 5MSPS
2 97.2dB 2.5MSPS
4 99.3dB 1.25MSPS
8 101.1dB 625kSPS
16 103.1dB 312.5kSPS
32 105.1dB 156.25kSPS
64 106.5dB 78.125kSPS
128 107.1dB 39.0625kSPS

ADS9326 ADS9327 ADC Output Example for Simple Average of 4 Samples in 2-Lane Data Interface Mode

Figure 7-12 ADC Output Example for Simple Average of 4 Samples in 2-Lane Data Interface Mode

The ADS932x supports simple averaging with low latency mode enabled. Figure 7-13 illustrates the timing diagram when simple averaging is used with low latency mode active.


ADS9326 ADS9327 ADC Output Example for Simple Average of 4 Samples in 2-Lane Data Interface Mode with Low Latency Mode Enabled

Figure 7-13 ADC Output Example for Simple Average of 4 Samples in 2-Lane Data Interface Mode with Low Latency Mode Enabled