SBAU416C November   2022  – March 2025 ADS9813 , ADS9817

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 ADS9813EVM and ADS9817EVM Quick Start Guide
    3. 2.3 Analog Interface
      1. 2.3.1 ADC Input SMA Connections
      2. 2.3.2 Voltage Reference
    4. 2.4 Digital Interface and Clock Inputs
      1. 2.4.1 Digital Interface Connections
      2. 2.4.2 Clock Select
    5. 2.5 Power Supplies
      1. 2.5.1 USB Power and When to Power the Board Externally
  7. 3Software
    1. 3.1 ADS9817EVM and ADS9813EVM Software Installation
      1. 3.1.1 USB Driver Installation
    2. 3.2 ADS9817EVM Software (ADS9817EVM-GUI)
      1. 3.2.1 Using the CONFIG Tab
      2. 3.2.2 Using the Capture Tab
      3. 3.2.3 Using the INL/DNL Tool
      4. 3.2.4 Using the Histogram Tab
    3. 3.3 ADS9813EVM Software (ADS98XXEVM-GUI)
      1. 3.3.1 Using Configuration Tab
      2. 3.3.2 Using the Data Capture Tab
      3. 3.3.3 Using the Linearity Analysis Tab
      4. 3.3.4 Using the Histogram Analysis Tab
  8. 4Hardware Design Files
    1. 4.1 Schematics
      1. 4.1.1 ADS9813EVM Schematics
      2. 4.1.2 ADS9817EVM Schematics
    2. 4.2 Layout
    3. 4.3 Bill of Materials (BOM)
      1. 4.3.1 ADS9813EVM Bill of Materials (BOM)
      2. 4.3.2 ADS9817EVM Bill of Materials (BOM)
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Related Documentation
  11. 7Revision History

2.4.2 Clock Select

The ADS9813EVM and ADS9817EVM use single-ended sampling clock for ADC conversions. The positive sampling clock input (SMPL_CLKP) is selected using jumper JP8. Install a shunt in the [2-3] position (default) to source the clock signal from the TSWDC155EVM through the FMC connector. This allows the user to select the clock frequency from the options listed in the EVM GUI.

An external clock source can also be used to control ADC conversions. Connect a low-jitter clock source to SMA connector J14 and install a shunt in the [1-2] position on JP8.

The negative source of the sample clock (SMPL_CLKM) can be sourced from either the FMC connector (FMC_SMPL_CLKM) or GND through R18 or R17, respectively. By default, R17 is populated and R18 is uninstalled.

ADS9813EVM, ADS9817EVM Sample Clock SelectionFigure 2-6 Sample Clock Selection