SBAU478 February   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Supplies
    2. 2.2 EVM Analog Input
    3. 2.3 ADC Circuit
    4. 2.4 Jumper Information
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layer Plots
    3. 3.3 Bill of Materials (BOM)
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.3 ADC Circuit

Figure 2-4 shows the connections to the ADC168M102R-SEP device. The AVDD and DVDD supplies are decoupled with 1μF capacitors. The analog inputs are supplied by the outputs of the OPA4H014-SEP circuits. The REFIO1 and REFIO2 pins require 22μF capacitors connected close to the pins. Header J5 provides a way to probe the digital communication pins with an oscilloscope or logic analyzer. Additionally, it provides a way to connect an external controller for use with the ADC168M102R-SEP.

ADC168M102REVM-PDK ADC168M102R-SEP Decoupling and Digital Interface Figure 2-4 ADC168M102R-SEP Decoupling and Digital Interface

By default, jumpers JP1 and JP2 are configured in the "CMx_EXT" position. Place the shunts to the "CMx_INT" position to use the output of the REFDACs from the REFIO pins as the input to the CMA or CMB pins.