1 Introduction

Electrification throughout the world has exploded in the last decade. Electric vehicles, clean energy in the form of solar PV and type III and IV wind, data centers, higher efficiency power supplies and more have all skyrocketed in demand, with designers racing to develop designs that are cutting edge while simultaneously refining those designs for better performance, lower cost, and smaller form factor. The United States government has set a high bar in this area, with the Department of Energy tasking companies to reach new milestones in these various areas, such as a 100kW/L power density target by 2025 (with even more stringent targets listed for 2030 and 2035) for high voltage power designs, with a simultaneous cost target of only $1.80/kW and efficiency target of 98%. Furthermore, the Department of Energy have provided several companies grants and incentives to perform research and development in this area to make sure the US remains a key competitor in these spaces.

These targets are not easy to achieve. As form factors continue to shrink, components must be placed continually closer to each other in proximity, and as a result the design problem becomes more complex to also include more cumbersome thermal management, as well as the handling of electromagnetic interference. In these systems, there are often multiple field-effect transistor (FET) devices switching at relatively high speeds in power quantities great enough to produce near-field emissions that can affect other electrical components in proximity. The designer's historic ability to potentially mitigate these issues by strategic placement of sensitive components away from these intentional radiators is removed, and designs must now be developed to effectively EMI harden integrated circuits and components on the PCB to achieve the lofty targets set forth by the desired specification.

In this paper, the TMCS112x and TMCS113x family of devices is used as an example in the derivation of an EMI hardened approach to circuit design. These components are examined at the pin level for the ability to attenuate both common-mode and differential-mode forms of noise. Layout is also examined and discussed, as layout in the high-frequency domain becomes of the utmost importance. Proper layout guidelines need to be followed, and layout optimized well before attempting the techniques discussed in this paper, as the use of ferrite beads and filters can only correct signals to a certain extent, and often come with design tradeoffs, including, but not limited to system losses, accuracy, additional board space (and therefore loss of power density), and additional cost.

Note that this analysis focuses primarily on conducted emissions, and radiated emissions analysis needs to also be examined for the most robust performance. Analysis is also only performed on the low voltage side of the TMCS device, and additional noise analysis can be necessary on the high voltage side at the device inputs to make sure of a performance designed for a specific design.