Making sure robustness against EMI starts with a good layout, not only for the TMCS112x/3x, but all components on the PCB. In general, boards containing 4-layers or more provide the best return path scenario, as ground planes on the inner layers provide a designed for return path for all signals; wherever traces were run, signal or power, there is always a return directly underneath the signal. However, newer designs are pushing higher power into the PCB, demanding new techniques be implemented to help manage the thermal problem. This can lead to scenarios such as inner plane replication which can segment ground planes, or designs reducing layer count down to 2 in an effort to further reduce cost in the system. Even though preventing the EMI aggressors is the best course of action is not always possible. In these scenarios, EMI-resilient design is possible, but additional steps and best practice must be considered to make sure of the designed for performance. In general, the best practice is to route return paths directly beneath the signal. In addition, consider the following best practices as you lay out the TMCS112x/3x in your design:

• If possible, use a 4 layer board. Create a GND plane on an internal layer for the purposes of providing a clean return path for all signals traced on the outer layers.
  • The best practice is to not route traces in the ground place at all. If this must happen, make sure the trace layout is optimized to keep splitting of the ground plane to a minimum, as this can reroute return paths through unwanted areas, or increase loop size in signals
• Isolate the device from high sources of EMI as much as possible. Fast switching inductors loops and high voltage switch nodes are of largest concern.
  • Inductance increases with length, and decreases with width. Therefore, high-frequency current paths need to be made as wide, and as short as possible.
• All capacitors need to be sized to 0402 or 0603 for the lowest ESR, for example, best high frequency response. Typically, the smallest footprint device can result in lowest parasitics, and therefore, these smaller options tend to perform better in high-EMI environments
  • At a minimum, make sure at least one bypass capacitor is used between the V+ and GND pins of the device.
  • If multiple bypass capacitors are used, make sure the lowest capacitance (which targets the highest frequencies) is placed closest to the device. This is performed to make sure that all HF content is removed prior to reaching the part. If the lowest capacitance were placed farthest from the part, HF content can potentially couple onto the trace beyond the capacitor and then migrate into the device.
• Shield signal traces with the respective return path if possible. In most cases, this can be the common GND. This technique can help reduce the antenna effects of unshielded traces. An example of this can be seen in Figure 3-11.

For designs where high CM noise is also present, additional isolation techniques through grounds can be used. Figure 3-12 shows an example of islanding the GND of the TMCS112x/3x. This technique effectively severs the noisy system GND from the device, and makes sure CM noise does not couple into the device. If CM noise is not present in the system, the TMCS112x/3x can be referenced to GND as normal, and capacitor C8 is not needed. The following practices need to also be noted if using this technique:

• Ferrite beads (L1, L2, L4, L5) needs to be sized as large as possible to maximize space between GND planes.
• The 100pF stitching cap between GNDs (C8) gives a return path for high frequency radiated noise
  • Without this cap, radiated noise can couple into the TMCS GND plane and see a high impedance return path to the MCU GND.
  • This can trap the HF noise and force the noise to couple into our device pins as these are lower impedance than the ferrite beads.
  • This capacitor provides a low impedance path at HF to return noise to MCU GND.
• Input capacitors C1, C5, and C6 are only needed if CM noise is measured in the system. Please place pads for all components in this schematic for troubleshooting.
• While not shown in the layout, a common-mode choke can be used in place of beads L1 and L4 to further limit common mode noise into the device. Usage of both ferrite beads and a choke is not necessary here, and can only further increase cost and component count.