SBOS576C May   2012  – September 2025 INA3221

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Basic ADC Functions
      2. 7.3.2 Alert Monitoring
        1. 7.3.2.1 Critical Alert
          1. 7.3.2.1.1 Summation Control Function
        2. 7.3.2.2 Warning Alert
        3. 7.3.2.3 Power-Valid Alert
        4. 7.3.2.4 Timing-Control Alert
        5. 7.3.2.5 Default Settings
      3. 7.3.3 Software Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Averaging Function
      2. 7.4.2 Multiple Channel Monitoring
        1. 7.4.2.1 Channel Configuration
        2. 7.4.2.2 Averaging and Conversion-Time Considerations
      3. 7.4.3 Filtering and Input Considerations
    5. 7.5 Programming
      1. 7.5.1 Bus Overview
        1. 7.5.1.1 Serial Bus Address
        2. 7.5.1.2 Serial Interface
      2. 7.5.2 Writing To and Reading From the INA3221
        1. 7.5.2.1 High-Speed I2C Mode
      3. 7.5.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Summary of Register Set
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1  Configuration Register (address = 00h) [reset = 7127h]
        2. 7.6.2.2  Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
        3. 7.6.2.3  Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
        4. 7.6.2.4  Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
        5. 7.6.2.5  Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
        6. 7.6.2.6  Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
        7. 7.6.2.7  Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
        8. 7.6.2.8  Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
        9. 7.6.2.9  Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
        10. 7.6.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
        11. 7.6.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
        12. 7.6.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
        13. 7.6.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
        14. 7.6.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
        15. 7.6.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
        16. 7.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
        17. 7.6.2.17 Power-valid Upper-limit Register (address = 10h) [reset = 2710h]
        18. 7.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
        19. 7.6.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
        20. 7.6.2.20 Die ID Register (address = FFh) [reset = 3220]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.2 Writing To and Reading From the INA3221

To access a specific INA3221 register, write the appropriate value to the register pointer. See Table 7-3 for a complete list of registers and corresponding addresses. The value for the register pointer, as shown in Figure 7-9, is the first byte transferred after the target address byte with the R/ W bit low. Every write operation to the INA3221 requires a register pointer value.

INA3221 Typical Register Pointer Set
A. The value of the Target Address Byte is determined by the A0 pin setting; see Table 7-1.
Figure 7-9 Typical Register Pointer Set

Register writes begin with the first byte transmitted by the controller. This byte is the target address, with the R/ W bit low. The INA3221 then acknowledges receipt of a valid address. The next byte transmitted by the controller is the register address that data are written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA3221 acknowledges receipt of each data byte. The controller terminates data transfer by generating a start or stop condition.

When reading from the INA3221, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, write a new value to the register pointer. This write is accomplished by issuing a target address byte with the R/ W bit low, followed by the register pointer byte. No additional data are required. The controller then generates a start condition and sends the target address byte with the R/ W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register pointer. This byte is followed by an acknowledge from the controller; then the target transmits the least significant byte. The controller acknowledges receipt of the data byte. The controller terminates data transfer by generating a not-acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA3221 retains the register pointer value until the value is changed by the next write operation.

Figure 7-10 and Figure 7-11 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte.

INA3221 Timing Diagram for Write Word Format
A. The value of the target address byte is determined by the A0 pin setting; see Table 7-1.
Figure 7-10 Timing Diagram for Write Word Format
INA3221 Timing Diagram for Read Word Format
A. The value of the target address byte is determined by the A0 pin setting; see Table 7-1.
B. Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 7-9.
C. The controller can also send an ACK.
Figure 7-11 Timing Diagram for Read Word Format

Figure 7-12 shows the timing diagram for the SMBus Alert response operation.

INA3221 Timing Diagram for SMBus Alert
A. The value of the Target Address Byte is determined by the A0 pin setting; see Table 7-1.
Figure 7-12 Timing Diagram for SMBus Alert