SCPS289B September   2024  – August 2026 TPLD1202

PRODUCTION DATA  

  1.   1
  2.   2
  3.   3
  4. 1 Features
  5. 2 Applications
  6. 3 Description
  7. 4 Pin Configuration and Functions
  8. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Supply Current Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  I2C Bus Timing Requirements
    9. 5.9  SPI Timing Requirements
    10. 5.10 Typical Characteristics
  9. 6 Parameter Measurement Information
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch With Reset/Set Macro-Cell
          1. 7.3.3.3.1 3-bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set Macro-Cell
          1. 7.3.3.5.1 4-bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing Blocks
        1. 7.3.4.1 3-bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 8-Bit Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Detector Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Oscillators
        1. 7.3.14.1 2kHz or 10kHz Selectable Frequency Oscillator
        2. 7.3.14.2 25MHz Fixed Frequency Oscillator
        3. 7.3.14.3 Oscillator Power Modes
      15. 7.3.15 Serial Communications
        1. 7.3.15.1 I2C Mode
        2. 7.3.15.2 SPI Mode
        3. 7.3.15.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP) and Programming Procedure
        3. 7.4.4.3 Intel HEX File Format
  11. 8 TPLD1202 Registers
    1. 8.1 TPLD1202_User Registers
    2. 8.2 TPLD1202_Cfg_0 Registers
    3. 8.3 TPLD1202_Cfg_1 Registers
  12. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  14. 11Revision History
  15. 12Mechanical, Packaging, and Orderable Information

8.1 TPLD1202_User Registers

Table 8-1 lists the memory-mapped registers for the TPLD1202_User registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 TPLD1202_USER Registers
OffsetAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0hDEVICE_ID0DEVICE_ID_MSB
1hDEVICE_ID1DEVICE_ID_LSB
2hDEVICE_ID2DEVICE_ID_RSVD
3hDEVICE_ID3DEVICE_ID_REV
4hPROG_ID0PROG_ID0
5hPROG_ID1PROG_ID1
6hPROG_ID2PROG_ID2
7hPROG_ID3PROG_ID3
10hCNT0_COUNTCNT0_COUNT
11hCNT1_COUNTCNT1_COUNT
12hCNT2_COUNTCNT2_COUNT
13hCNT3_COUNTCNT3_COUNT
14hCNT4_COUNTCNT4_COUNT
15hCNT5_COUNTCNT5_COUNT
16hCNT6_COUNTCNT6_COUNT
17hCNT7_COUNTCNT7_COUNT
18hCNT8_COUNTCNT8_COUNT
19hCNT9_COUNTCNT9_COUNT
20hCNT0_DATACNT0_DATA
21hCNT1_DATACNT1_DATA
22hCNT2_DATACNT2_DATA
23hCNT3_DATACNT3_DATA
24hCNT4_DATACNT4_DATA
25hCNT5_DATACNT5_DATA
26hCNT6_DATACNT6_DATA
27hCNT7_DATACNT7_DATA
28hCNT8_DATACNT8_DATA
29hCNT9_DATACNT9_DATA
30hWDT_TIMEOUT_DATAWATCHDOG_TIMEOUT_DATA
31hWDT_OUTPUT_DATAWATCHDOG_OUTPUT_DATA
32hWDT_STATUSRESERVEDWDT_STATUS
40hPGEN_DATA_LSBPGEN_DATA_LSB
41hPGEN_DATA_MSBPGEN_DATA_MSB
50hSTATE_MACHINERESERVEDCURRENT_STATE
51hSTATE0_OUTSTATE0_OUT
52hSTATE1_OUTSTATE1_OUT
53hSTATE2_OUTSTATE2_OUT
54hSTATE3_OUTSTATE3_OUT
55hSTATE4_OUTSTATE4_OUT
56hSTATE5_OUTSTATE5_OUT
57hSTATE6_OUTSTATE6_OUT
58hSTATE7_OUTSTATE7_OUT
70hVREF_McACMP0RESERVEDVREF_McACMP0
71hVREF_McACMP1RESERVEDVREF_McACMP1
72hVREF_McACMP2RESERVEDVREF_McACMP2
73hVREF_McACMP3RESERVEDVREF_McACMP3
E0hVIRTUAL_INPUTVIRTUAL_IN
E1hVIRTUAL_OUTPUTVIRTUAL_OUT
FDhSER_COMM_CFGRESERVEDADDR_INC
FEhCRC_STATUSERR_CNTRESERVEDERR_FLAG
FFhSER_COMM_WR_MASKSER_COMM_WR_MASK

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 TPLD1202_User Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.1 DEVICE_ID0 Register (Offset = 0h) [Reset = 12h]

DEVICE_ID0 is shown in Table 8-3.

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Table 8-3 DEVICE_ID0 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_MSBR12h

8.1.2 DEVICE_ID1 Register (Offset = 1h) [Reset = 02h]

DEVICE_ID1 is shown in Table 8-4.

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Table 8-4 DEVICE_ID1 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_LSBR2h

8.1.3 DEVICE_ID2 Register (Offset = 2h) [Reset = 00h]

DEVICE_ID2 is shown in Table 8-5.

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Table 8-5 DEVICE_ID2 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_RSVDR0h

8.1.4 DEVICE_ID3 Register (Offset = 3h) [Reset = 20h]

DEVICE_ID3 is shown in Table 8-6.

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Table 8-6 DEVICE_ID3 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_REVR20h

8.1.5 PROG_ID0 Register (Offset = 4h) [Reset = X0h]

PROG_ID0 is shown in Table 8-7.

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Table 8-7 PROG_ID0 Register Field Descriptions
BitFieldTypeResetDescription
7:0PROG_ID0RXh

8.1.6 PROG_ID1 Register (Offset = 5h) [Reset = X0h]

PROG_ID1 is shown in Table 8-8.

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Table 8-8 PROG_ID1 Register Field Descriptions
BitFieldTypeResetDescription
7:0PROG_ID1RXh

8.1.7 PROG_ID2 Register (Offset = 6h) [Reset = X0h]

PROG_ID2 is shown in Table 8-9.

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Table 8-9 PROG_ID2 Register Field Descriptions
BitFieldTypeResetDescription
7:0PROG_ID2RXh

8.1.8 PROG_ID3 Register (Offset = 7h) [Reset = X0h]

PROG_ID3 is shown in Table 8-10.

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Table 8-10 PROG_ID3 Register Field Descriptions
BitFieldTypeResetDescription
7:0PROG_ID3RXh

8.1.9 CNT0_COUNT Register (Offset = 10h) [Reset = X0h]

CNT0_COUNT is shown in Table 8-11.

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Table 8-11 CNT0_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT0_COUNTRXh

8.1.10 CNT1_COUNT Register (Offset = 11h) [Reset = X0h]

CNT1_COUNT is shown in Table 8-12.

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Table 8-12 CNT1_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT1_COUNTRXh

8.1.11 CNT2_COUNT Register (Offset = 12h) [Reset = X0h]

CNT2_COUNT is shown in Table 8-13.

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Table 8-13 CNT2_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT2_COUNTRXh

8.1.12 CNT3_COUNT Register (Offset = 13h) [Reset = X0h]

CNT3_COUNT is shown in Table 8-14.

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Table 8-14 CNT3_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT3_COUNTRXh

8.1.13 CNT4_COUNT Register (Offset = 14h) [Reset = X0h]

CNT4_COUNT is shown in Table 8-15.

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Table 8-15 CNT4_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT4_COUNTRXh

8.1.14 CNT5_COUNT Register (Offset = 15h) [Reset = X0h]

CNT5_COUNT is shown in Table 8-16.

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Table 8-16 CNT5_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT5_COUNTRXh

8.1.15 CNT6_COUNT Register (Offset = 16h) [Reset = X0h]

CNT6_COUNT is shown in Table 8-17.

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Table 8-17 CNT6_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT6_COUNTRXh

8.1.16 CNT7_COUNT Register (Offset = 17h) [Reset = X0h]

CNT7_COUNT is shown in Table 8-18.

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Table 8-18 CNT7_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT7_COUNTRXh

8.1.17 CNT8_COUNT Register (Offset = 18h) [Reset = X0h]

CNT8_COUNT is shown in Table 8-19.

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Table 8-19 CNT8_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT8_COUNTRXh

8.1.18 CNT9_COUNT Register (Offset = 19h) [Reset = X0h]

CNT9_COUNT is shown in Table 8-20.

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Table 8-20 CNT9_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT9_COUNTRXh

8.1.19 CNT0_DATA Register (Offset = 20h) [Reset = X0h]

CNT0_DATA is shown in Table 8-21.

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Table 8-21 CNT0_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT0_DATAR/WXh

8.1.20 CNT1_DATA Register (Offset = 21h) [Reset = X0h]

CNT1_DATA is shown in Table 8-22.

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Table 8-22 CNT1_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT1_DATAR/WXh

8.1.21 CNT2_DATA Register (Offset = 22h) [Reset = X0h]

CNT2_DATA is shown in Table 8-23.

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Table 8-23 CNT2_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT2_DATAR/WXh

8.1.22 CNT3_DATA Register (Offset = 23h) [Reset = X0h]

CNT3_DATA is shown in Table 8-24.

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Table 8-24 CNT3_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT3_DATAR/WXh

8.1.23 CNT4_DATA Register (Offset = 24h) [Reset = X0h]

CNT4_DATA is shown in Table 8-25.

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Table 8-25 CNT4_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT4_DATAR/WXh

8.1.24 CNT5_DATA Register (Offset = 25h) [Reset = X0h]

CNT5_DATA is shown in Table 8-26.

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Table 8-26 CNT5_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT5_DATAR/WXh

8.1.25 CNT6_DATA Register (Offset = 26h) [Reset = X0h]

CNT6_DATA is shown in Table 8-27.

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Table 8-27 CNT6_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT6_DATAR/WXh

8.1.26 CNT7_DATA Register (Offset = 27h) [Reset = X0h]

CNT7_DATA is shown in Table 8-28.

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Table 8-28 CNT7_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT7_DATAR/WXh

8.1.27 CNT8_DATA Register (Offset = 28h) [Reset = X0h]

CNT8_DATA is shown in Table 8-29.

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Table 8-29 CNT8_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT8_DATAR/WXh

8.1.28 CNT9_DATA Register (Offset = 29h) [Reset = X0h]

CNT9_DATA is shown in Table 8-30.

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Table 8-30 CNT9_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT9_DATAR/WXh

8.1.29 WDT_TIMEOUT_DATA Register (Offset = 30h) [Reset = X0h]

WDT_TIMEOUT_DATA is shown in Table 8-31.

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Table 8-31 WDT_TIMEOUT_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0WATCHDOG_TIMEOUT_DATAR/WXh

8.1.30 WDT_OUTPUT_DATA Register (Offset = 31h) [Reset = X0h]

WDT_OUTPUT_DATA is shown in Table 8-32.

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Table 8-32 WDT_OUTPUT_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0WATCHDOG_OUTPUT_DATAR/WXh

8.1.31 WDT_STATUS Register (Offset = 32h) [Reset = X0h]

WDT_STATUS is shown in Table 8-33.

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Table 8-33 WDT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0WDT_STATUSR/WXh Watchdog fault output

8.1.32 PGEN_DATA_LSB Register (Offset = 40h) [Reset = X0h]

PGEN_DATA_LSB is shown in Table 8-34.

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Table 8-34 PGEN_DATA_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0PGEN_DATA_LSBR/WXh

8.1.33 PGEN_DATA_MSB Register (Offset = 41h) [Reset = X0h]

PGEN_DATA_MSB is shown in Table 8-35.

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Table 8-35 PGEN_DATA_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0PGEN_DATA_MSBR/WXh

8.1.34 STATE_MACHINE Register (Offset = 50h) [Reset = X0h]

STATE_MACHINE is shown in Table 8-36.

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Table 8-36 STATE_MACHINE Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0h Reserved
2:0CURRENT_STATERXh

8.1.35 STATE0_OUT Register (Offset = 51h) [Reset = X0h]

STATE0_OUT is shown in Table 8-37.

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Table 8-37 STATE0_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE0_OUTR/WXh

8.1.36 STATE1_OUT Register (Offset = 52h) [Reset = X0h]

STATE1_OUT is shown in Table 8-38.

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Table 8-38 STATE1_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE1_OUTR/WXh

8.1.37 STATE2_OUT Register (Offset = 53h) [Reset = X0h]

STATE2_OUT is shown in Table 8-39.

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Table 8-39 STATE2_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE2_OUTR/WXh

8.1.38 STATE3_OUT Register (Offset = 54h) [Reset = X0h]

STATE3_OUT is shown in Table 8-40.

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Table 8-40 STATE3_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE3_OUTR/WXh

8.1.39 STATE4_OUT Register (Offset = 55h) [Reset = X0h]

STATE4_OUT is shown in Table 8-41.

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Table 8-41 STATE4_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE4_OUTR/WXh

8.1.40 STATE5_OUT Register (Offset = 56h) [Reset = X0h]

STATE5_OUT is shown in Table 8-42.

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Table 8-42 STATE5_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE5_OUTR/WXh

8.1.41 STATE6_OUT Register (Offset = 57h) [Reset = X0h]

STATE6_OUT is shown in Table 8-43.

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Table 8-43 STATE6_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE6_OUTR/WXh

8.1.42 STATE7_OUT Register (Offset = 58h) [Reset = X0h]

STATE7_OUT is shown in Table 8-44.

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Table 8-44 STATE7_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE7_OUTR/WXh

8.1.43 VREF_McACMP0 Register (Offset = 70h) [Reset = X0h]

VREF_McACMP0 is shown in Table 8-45.

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Table 8-45 VREF_McACMP0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP0R/WXh

8.1.44 VREF_McACMP1 Register (Offset = 71h) [Reset = X0h]

VREF_McACMP1 is shown in Table 8-46.

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Table 8-46 VREF_McACMP1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP1R/WXh

8.1.45 VREF_McACMP2 Register (Offset = 72h) [Reset = X0h]

VREF_McACMP2 is shown in Table 8-47.

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Table 8-47 VREF_McACMP2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP2R/WXh

8.1.46 VREF_McACMP3 Register (Offset = 73h) [Reset = X0h]

VREF_McACMP3 is shown in Table 8-48.

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Table 8-48 VREF_McACMP3 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP3R/WXh

8.1.47 VIRTUAL_INPUT Register (Offset = E0h) [Reset = X0h]

VIRTUAL_INPUT is shown in Table 8-49.

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Table 8-49 VIRTUAL_INPUT Register Field Descriptions
BitFieldTypeResetDescription
7:0VIRTUAL_INR/WXh

8.1.48 VIRTUAL_OUTPUT Register (Offset = E1h) [Reset = X0h]

VIRTUAL_OUTPUT is shown in Table 8-50.

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Table 8-50 VIRTUAL_OUTPUT Register Field Descriptions
BitFieldTypeResetDescription
7:0VIRTUAL_OUTRXh

8.1.49 SER_COMM_CFG Register (Offset = FDh) [Reset = X0h]

SER_COMM_CFG is shown in Table 8-51.

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Table 8-51 SER_COMM_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0ADDR_INCR/WXh Address auto-incrementing disable select
  • 0h = Enabled
  • 1h = Disabled

8.1.50 CRC_STATUS Register (Offset = FEh) [Reset = X0h]

CRC_STATUS is shown in Table 8-52.

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Table 8-52 CRC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:5ERR_CNTR0h
4:1RESERVEDR0h Reserved
0ERR_FLAGR/WXh

8.1.51 SER_COMM_WR_MASK Register (Offset = FFh) [Reset = X0h]

SER_COMM_WR_MASK is shown in Table 8-53.

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Table 8-53 SER_COMM_WR_MASK Register Field Descriptions
BitFieldTypeResetDescription
7:0SER_COMM_WR_MASKR/WXh