SCPS289 Data sheet

SCPS289B September 2024 – August 2026 TPLD1202

PRODUCTION DATA

8.3 TPLD1202_Cfg_1 Registers

Table 8-169 lists the memory-mapped registers for the TPLD1202_Cfg_1 registers. All register offset addresses not listed in Table 8-169 should be considered as reserved locations and the register contents should not be modified.

Table 8-169 TPLD1202_CFG_1 Registers

Offset	Acronym	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
300h	GPI_CFG	RESERVED	PULL_UP_EN	RES_SEL		RESERVED		IN_CTRL
301h	GPIO1_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
302h	GPIO2_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
303h	GPIO3_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
304h	GPIO4_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
305h	GPIO5_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
306h	GPIO6_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
307h	GPIO7_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
308h	GPIO8_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
309h	GPIO9_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
320h	VIO_SEL_0	V_IN7	V_IN6	V_IN5	V_IN4	V_IN3	V_IN2	V_IN1	V_IN0
324h	LUT_FS_0	RESERVED					LUT2_2_FS	LUT2_1_FS	LUT2_0_FS
325h	LUT_FS_1	LUT3_7_FS	LUT3_6_FS	LUT3_5_FS	LUT3_4_FS	LUT3_3_FS	LUT3_2_FS	LUT3_1_FS	LUT3_0_FS
326h	LUT_FS_2	RESERVED							LUT4_0_FS
328h	LUT2_0_CFG	RESERVED				BIT3	BIT2	BIT1	BIT0
329h	LUT2_1_CFG	RESERVED				BIT3	BIT2	BIT1	BIT0
32Eh	LUT2_2_CFG0	RESERVED		PGEN_RST	RESERVED	BITS3_0
32Fh	LUT2_2_CFG1	PGEN_DATA_LSB
330h	LUT2_2_CFG2	PGEN_DATA_MSB
334h	LUT3_0_CFG	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
335h	LUT3_1_CFG	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
336h	LUT3_2_CFG	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
337h	LUT3_3_CFG	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
338h	LUT3_4_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
339h	LUT3_4_CFG1	SR0_INIT
33Ah	LUT3_5_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
33Bh	LUT3_5_CFG1	SR1_INIT
33Ch	LUT3_6_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
33Dh	LUT3_6_CFG1	SR2_INIT
33Eh	LUT3_7_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
33Fh	LUT3_7_CFG1	SR3_INIT
344h	LUT4_0_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
345h	LUT4_0_CFG1	LUT4_0_MSB
354h	LUT3_8_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
355h	LUT3_8_CFG1	CNT_DATA
356h	LUT3_8_CFG2	CLK_SEL				MODE_SEL
357h	LUT3_8_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
358h	LUT3_8_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
359h	LUT3_9_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
35Ah	LUT3_9_CFG1	CNT_DATA
35Bh	LUT3_9_CFG2	CLK_SEL				MODE_SEL
35Ch	LUT3_9_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
35Dh	LUT3_9_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
35Eh	LUT3_10_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
35Fh	LUT3_10_CFG1	CNT_DATA
360h	LUT3_10_CFG2	CLK_SEL				MODE_SEL
361h	LUT3_10_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
362h	LUT3_10_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
363h	LUT3_11_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
364h	LUT3_11_CFG1	CNT_DATA
365h	LUT3_11_CFG2	CLK_SEL				MODE_SEL
366h	LUT3_11_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
367h	LUT3_11_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
368h	LUT3_12_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
369h	LUT3_12_CFG1	CNT_DATA
36Ah	LUT3_12_CFG2	CLK_SEL				MODE_SEL
36Bh	LUT3_12_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
36Ch	LUT3_12_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
36Dh	LUT3_13_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
36Eh	LUT3_13_CFG1	CNT_DATA
36Fh	LUT3_13_CFG2	CLK_SEL				MODE_SEL
370h	LUT3_13_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
371h	LUT3_13_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
37Eh	CNT6_FSM0_CFG0	CNT_DATA
37Fh	CNT6_FSM0_CFG1	CLK_SEL				MODE_SEL
380h	CNT6_FSM0_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
381h	CNT7_FSM1_CFG0	CNT_DATA
382h	CNT7_FSM1_CFG1	CLK_SEL				MODE_SEL
383h	CNT7_FSM1_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
384h	CNT8_FSM2_CFG0	CNT_DATA
385h	CNT8_FSM2_CFG1	CLK_SEL				MODE_SEL
386h	CNT8_FSM2_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
387h	CNT9_FSM3_CFG0	CNT_DATA
388h	CNT9_FSM3_CFG1	CLK_SEL				MODE_SEL
389h	CNT9_FSM3_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
38Ah	PWM_GEN0_CFG	PWM_EN	RESERVED			TDB_SEL		OUTP_POL	OUTN_POL
38Bh	PWM_GEN1_CFG	PWM_EN	RESERVED			TDB_SEL		OUTP_POL	OUTN_POL
38Ch	PWM_GEN2_CFG	PWM_EN	RESERVED			TDB_SEL		OUTP_POL	OUTN_POL
38Dh	PWM_GEN3_CFG	PWM_EN	RESERVED			TDB_SEL		OUTP_POL	OUTN_POL
38Eh	PWM_SRC_CFG	PWM3_DATA_SEL		PWM2_DATA_SEL		PWM1_DATA_SEL		PWM0_DATA_SEL
38Fh	SM_CFG0	RESERVED	SM_S1_IN0			RESERVED	SM_S0_IN0
390h	SM_CFG1	RESERVED	SM_S1_IN1			RESERVED	SM_S0_IN1
391h	SM_CFG2	RESERVED
392h	SM_CFG3	RESERVED	SM_S3_IN0			RESERVED	SM_S2_IN0
393h	SM_CFG4	RESERVED	SM_S3_IN1			RESERVED	SM_S2_IN1
394h	SM_CFG5	RESERVED
395h	SM_CFG6	RESERVED	SM_S5_IN0			RESERVED	SM_S4_IN0
396h	SM_CFG7	RESERVED	SM_S5_IN1			RESERVED	SM_S4_IN1
397h	SM_CFG8	RESERVED
398h	SM_CFG9	RESERVED	SM_S7_IN0			RESERVED	SM_S6_IN0
399h	SM_CFG10	RESERVED	SM_S7_IN1			RESERVED	SM_S6_IN1
39Ah	SM_CFG11	SM_SYNC_EN	RESERVED
3A7h	SM_CFG12	SM_CLK_SEL				MODE_SEL	SM_INIT_STATE
3A8h	SM_CFG13	S0_OUT_CFG
3A9h	SM_CFG14	S1_OUT_CFG
3AAh	SM_CFG15	S2_OUT_CFG
3ABh	SM_CFG16	S3_OUT_CFG
3ACh	SM_CFG17	S4_OUT_CFG
3ADh	SM_CFG18	S5_OUT_CFG
3AEh	SM_CFG19	S6_OUT_CFG
3AFh	SM_CFG20	S7_OUT_CFG
3B8h	WDT_CFG0	WDT_TIMEOUT_DATA
3B9h	WDT_CFG1	WDT_OUT_DATA
3BAh	WDT_CFG2	WDT_CLK_SEL				RESERVED	WDT_EN	WDT_100X_EN	WDT_EN_SEL
3BBh	PFLT_CFG	RESERVED		PFLT_DLY_SEL		PFLT_POL	RESERVED	PFLT_EDGE_SEL
3BDh	FLT_CFG	RESERVED				FLT_POL	RESERVED	FLT_EDGE_SEL
3BEh	OSC0_CFG0	RESERVED	CTRL_SRC	CTRL_SEL	SRC_SEL	PDIV		FREQ_SEL	PWR_MODE
3BFh	OSC0_CFG1	OUT1_EN	OUT1_DIV			OUT0_EN	OUT0_DIV
3C0h	OSC1_CFG0	SU_DLY	CTRL_SRC	CTRL_SEL	SRC_SEL	PDIV			PWR_MODE
3C1h	OSC1_CFG1	RESERVED				OUT_EN	OUT_DIV
3C5h	OSC1_CG	OSC1_DIV3	OSC1_DIV512	OSC1_DIV64	OSC1_DIV24	OSC1_DIV12	OSC1_DIV8	OSC1_DIV4	OSC1_DIV2
3CFh	MCACMP_CFG0	TS_INP_EN	VCC_INP_EN	SYNC_EN	MCS_MODE	CH_EN		RESERVED	MCS_EN
3D0h	MCACMP_CFG1	RESERVED					EDGE_SEL	MCS_CLK_SEL
3D1h	MCACMP_CH0_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3D2h	MCACMP_CH0_CFG1	RESERVED		VREF_SEL
3D6h	MCACMP_CH1_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3D7h	MCACMP_CH1_CFG1	RESERVED		VREF_SEL
3DBh	MCACMP_CH2_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3DCh	MCACMP_CH2_CFG1	RESERVED		VREF_SEL
3E0h	MCACMP_CH3_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3E1h	MCACMP_CH3_CFG1	RESERVED		VREF_SEL
3F2h	SER_COMM_CFG0	I2C_ADDR_SRC_SEL				I2C_IO_LAT	I2C_RST_EN	I2C_EN	SPI_EN
3F3h	SER_COMM_CFG1	I2C_ADDR_MSB				I2C_ADDR_LSB			RESERVED
3F7h	MISC_CFG0	GPIO_QC	CFG_RD_LCK	CFG_WR_LCK	OTP_WR_LCK	USER_LCK		RESERVED
3F8h	MISC_CFG1	RESERVED	VBG_CTRL			RESERVED	PREBIAS_CTRL
3F9h	MISC_CFG2	RESERVED							RD_DATA_SYNC
3FAh	DEVICE_ID4	DEVICE_ID4
3FBh	DEVICE_ID5	DEVICE_ID5
3FCh	DEVICE_ID6	DEVICE_ID6
3FDh	DEVICE_ID7	DEVICE_ID7
3FEh	CRC_LSB	CRC_LSB
3FFh	CRC_MSB	CRC_MSB

Complex bit access types are encoded to fit into small table cells. Table 8-170 shows the codes that are used for access types in this section.

Table 8-170 TPLD1202_Cfg_1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.3.1 GPI_CFG Register (Offset = 300h) [Reset = XXh]

GPI_CFG is shown in Table 8-171.

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Table 8-171 GPI_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	RESERVED	R	0h	Reserved
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

8.3.2 GPIO1_CFG Register (Offset = 301h) [Reset = X0h]

GPIO1_CFG is shown in Table 8-172.

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Table 8-172 GPIO1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 4X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

8.3.3 GPIO2_CFG Register (Offset = 302h) [Reset = X0h]

GPIO2_CFG is shown in Table 8-173.

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Table 8-173 GPIO2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 4X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

8.3.4 GPIO3_CFG Register (Offset = 303h) [Reset = XXh]

GPIO3_CFG is shown in Table 8-174.

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Table 8-174 GPIO3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

8.3.5 GPIO4_CFG Register (Offset = 304h) [Reset = XXh]

GPIO4_CFG is shown in Table 8-175.

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Table 8-175 GPIO4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

8.3.6 GPIO5_CFG Register (Offset = 305h) [Reset = X0h]

GPIO5_CFG is shown in Table 8-176.

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Table 8-176 GPIO5_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

8.3.7 GPIO6_CFG Register (Offset = 306h) [Reset = X0h]

GPIO6_CFG is shown in Table 8-177.

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Table 8-177 GPIO6_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

8.3.8 GPIO7_CFG Register (Offset = 307h) [Reset = X0h]

GPIO7_CFG is shown in Table 8-178.

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Table 8-178 GPIO7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

8.3.9 GPIO8_CFG Register (Offset = 308h) [Reset = XXh]

GPIO8_CFG is shown in Table 8-179.

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Table 8-179 GPIO8_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

8.3.10 GPIO9_CFG Register (Offset = 309h) [Reset = XXh]

GPIO9_CFG is shown in Table 8-180.

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Table 8-180 GPIO9_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

8.3.11 VIO_SEL_0 Register (Offset = 320h) [Reset = X0h]

VIO_SEL_0 is shown in Table 8-181.

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Table 8-181 VIO_SEL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	V_IN7	R/W	0h	0h = IO9 1h = V_IN7
6	V_IN6	R/W	0h	0h = IO7 1h = V_IN6
5	V_IN5	R/W	0h	0h = IO6 1h = V_IN5
4	V_IN4	R/W	0h	0h = IO5 1h = V_IN4
3	V_IN3	R/W	Xh	0h = IO4 1h = V_IN3
2	V_IN2	R/W	Xh	0h = IO3 1h = V_IN2
1	V_IN1	R/W	Xh	0h = IO2 1h = V_IN1
0	V_IN0	R/W	Xh	0h = IO1 1h = V_IN0

8.3.12 LUT_FS_0 Register (Offset = 324h) [Reset = 0Xh]

LUT_FS_0 is shown in Table 8-182.

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Table 8-182 LUT_FS_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R	0h	Reserved
2	LUT2_2_FS	R/W	Xh	0h = LUT 1h = PGEN
1	LUT2_1_FS	R/W	Xh	0h = LUT 1h = DFF
0	LUT2_0_FS	R/W	Xh	0h = LUT 1h = DFF

8.3.13 LUT_FS_1 Register (Offset = 325h) [Reset = X0h]

LUT_FS_1 is shown in Table 8-183.

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Table 8-183 LUT_FS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	LUT3_7_FS	R/W	0h	0h = LUT 1h = DFF / SR
6	LUT3_6_FS	R/W	0h	0h = LUT 1h = DFF / SR
5	LUT3_5_FS	R/W	0h	0h = LUT 1h = DFF / SR
4	LUT3_4_FS	R/W	0h	0h = LUT 1h = DFF / SR
3	LUT3_3_FS	R/W	Xh	0h = LUT 1h = DFF
2	LUT3_2_FS	R/W	Xh	0h = LUT 1h = DFF
1	LUT3_1_FS	R/W	Xh	0h = LUT 1h = DFF
0	LUT3_0_FS	R/W	Xh	0h = LUT 1h = DFF

8.3.14 LUT_FS_2 Register (Offset = 326h) [Reset = 0Xh]

LUT_FS_2 is shown in Table 8-184.

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Table 8-184 LUT_FS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0h	Reserved
0	LUT4_0_FS	R/W	Xh	0h = LUT 1h = DFF

8.3.15 LUT2_0_CFG Register (Offset = 328h) [Reset = X0h]

LUT2_0_CFG is shown in Table 8-185.

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Table 8-185 LUT2_0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	BIT3	R/W	Xh	LUT2[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT2[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT2[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT2[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.16 LUT2_1_CFG Register (Offset = 329h) [Reset = X0h]

LUT2_1_CFG is shown in Table 8-186.

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Table 8-186 LUT2_1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	BIT3	R/W	Xh	LUT2[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT2[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT2[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT2[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.17 LUT2_2_CFG0 Register (Offset = 32Eh) [Reset = XXh]

LUT2_2_CFG0 is shown in Table 8-187.

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Table 8-187 LUT2_2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	PGEN_RST	R/W	Xh	OTP_SPARE or PGEN RST LVL 0h = Low 1h = High
4	RESERVED	R	0h	Reserved
3:0	BITS3_0	R/W	Xh	LUT2[3:0] or PGEN SIZE 0h = 1 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8 8h = 9 9h = 10 Ah = 11 Bh = 12 Ch = 13 Dh = 14 Eh = 15 Fh = 16

8.3.18 LUT2_2_CFG1 Register (Offset = 32Fh) [Reset = X0h]

LUT2_2_CFG1 is shown in Table 8-188.

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Table 8-188 LUT2_2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_DATA_LSB	R/W	Xh	PGEN_DATA[7:0]

8.3.19 LUT2_2_CFG2 Register (Offset = 330h) [Reset = X0h]

LUT2_2_CFG2 is shown in Table 8-189.

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Table 8-189 LUT2_2_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_DATA_MSB	R/W	Xh	PGEN_DATA[15:8]

8.3.20 LUT3_0_CFG Register (Offset = 334h) [Reset = X0h]

LUT3_0_CFG is shown in Table 8-190.

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Table 8-190 LUT3_0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.21 LUT3_1_CFG Register (Offset = 335h) [Reset = X0h]

LUT3_1_CFG is shown in Table 8-191.

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Table 8-191 LUT3_1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.22 LUT3_2_CFG Register (Offset = 336h) [Reset = X0h]

LUT3_2_CFG is shown in Table 8-192.

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Table 8-192 LUT3_2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.23 LUT3_3_CFG Register (Offset = 337h) [Reset = X0h]

LUT3_3_CFG is shown in Table 8-193.

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Table 8-193 LUT3_3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.24 LUT3_4_CFG0 Register (Offset = 338h) [Reset = X0h]

LUT3_4_CFG0 is shown in Table 8-194.

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Table 8-194 LUT3_4_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.25 LUT3_4_CFG1 Register (Offset = 339h) [Reset = X0h]

LUT3_4_CFG1 is shown in Table 8-195.

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Table 8-195 LUT3_4_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SR0_INIT	R/W	Xh	DFF / SR INIT VAL

8.3.26 LUT3_5_CFG0 Register (Offset = 33Ah) [Reset = X0h]

LUT3_5_CFG0 is shown in Table 8-196.

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Table 8-196 LUT3_5_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.27 LUT3_5_CFG1 Register (Offset = 33Bh) [Reset = X0h]

LUT3_5_CFG1 is shown in Table 8-197.

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Table 8-197 LUT3_5_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SR1_INIT	R/W	Xh	DFF / SR INIT VAL

8.3.28 LUT3_6_CFG0 Register (Offset = 33Ch) [Reset = X0h]

LUT3_6_CFG0 is shown in Table 8-198.

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Table 8-198 LUT3_6_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.29 LUT3_6_CFG1 Register (Offset = 33Dh) [Reset = X0h]

LUT3_6_CFG1 is shown in Table 8-199.

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Table 8-199 LUT3_6_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SR2_INIT	R/W	Xh	DFF / SR INIT VAL

8.3.30 LUT3_7_CFG0 Register (Offset = 33Eh) [Reset = X0h]

LUT3_7_CFG0 is shown in Table 8-200.

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Table 8-200 LUT3_7_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.31 LUT3_7_CFG1 Register (Offset = 33Fh) [Reset = X0h]

LUT3_7_CFG1 is shown in Table 8-201.

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Table 8-201 LUT3_7_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SR3_INIT	R/W	Xh	DFF / SR INIT VAL

8.3.32 LUT4_0_CFG0 Register (Offset = 344h) [Reset = X0h]

LUT4_0_CFG0 is shown in Table 8-202.

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Table 8-202 LUT4_0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT4[7]
6	BIT6	R/W	0h	LUT4[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT4[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT4[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT4[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT4[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT4[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT4[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.33 LUT4_0_CFG1 Register (Offset = 345h) [Reset = X0h]

LUT4_0_CFG1 is shown in Table 8-203.

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Table 8-203 LUT4_0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LUT4_0_MSB	R/W	Xh	LUT4_0[15:8]

8.3.34 LUT3_8_CFG0 Register (Offset = 354h) [Reset = X0h]

LUT3_8_CFG0 is shown in Table 8-204.

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Table 8-204 LUT3_8_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.35 LUT3_8_CFG1 Register (Offset = 355h) [Reset = X0h]

LUT3_8_CFG1 is shown in Table 8-205.

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Table 8-205 LUT3_8_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.36 LUT3_8_CFG2 Register (Offset = 356h) [Reset = X0h]

LUT3_8_CFG2 is shown in Table 8-206.

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Table 8-206 LUT3_8_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.37 LUT3_8_CFG3 Register (Offset = 357h) [Reset = X0h]

LUT3_8_CFG3 is shown in Table 8-207.

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Table 8-207 LUT3_8_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.38 LUT3_8_CFG4 Register (Offset = 358h) [Reset = XXh]

LUT3_8_CFG4 is shown in Table 8-208.

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Table 8-208 LUT3_8_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

8.3.39 LUT3_9_CFG0 Register (Offset = 359h) [Reset = X0h]

LUT3_9_CFG0 is shown in Table 8-209.

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Table 8-209 LUT3_9_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.40 LUT3_9_CFG1 Register (Offset = 35Ah) [Reset = X0h]

LUT3_9_CFG1 is shown in Table 8-210.

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Table 8-210 LUT3_9_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.41 LUT3_9_CFG2 Register (Offset = 35Bh) [Reset = X0h]

LUT3_9_CFG2 is shown in Table 8-211.

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Table 8-211 LUT3_9_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.42 LUT3_9_CFG3 Register (Offset = 35Ch) [Reset = X0h]

LUT3_9_CFG3 is shown in Table 8-212.

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Table 8-212 LUT3_9_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.43 LUT3_9_CFG4 Register (Offset = 35Dh) [Reset = XXh]

LUT3_9_CFG4 is shown in Table 8-213.

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Table 8-213 LUT3_9_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

8.3.44 LUT3_10_CFG0 Register (Offset = 35Eh) [Reset = X0h]

LUT3_10_CFG0 is shown in Table 8-214.

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Table 8-214 LUT3_10_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.45 LUT3_10_CFG1 Register (Offset = 35Fh) [Reset = X0h]

LUT3_10_CFG1 is shown in Table 8-215.

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Table 8-215 LUT3_10_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.46 LUT3_10_CFG2 Register (Offset = 360h) [Reset = X0h]

LUT3_10_CFG2 is shown in Table 8-216.

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Table 8-216 LUT3_10_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.47 LUT3_10_CFG3 Register (Offset = 361h) [Reset = X0h]

LUT3_10_CFG3 is shown in Table 8-217.

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Table 8-217 LUT3_10_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.48 LUT3_10_CFG4 Register (Offset = 362h) [Reset = XXh]

LUT3_10_CFG4 is shown in Table 8-218.

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Table 8-218 LUT3_10_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

8.3.49 LUT3_11_CFG0 Register (Offset = 363h) [Reset = X0h]

LUT3_11_CFG0 is shown in Table 8-219.

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Table 8-219 LUT3_11_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.50 LUT3_11_CFG1 Register (Offset = 364h) [Reset = X0h]

LUT3_11_CFG1 is shown in Table 8-220.

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Table 8-220 LUT3_11_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.51 LUT3_11_CFG2 Register (Offset = 365h) [Reset = X0h]

LUT3_11_CFG2 is shown in Table 8-221.

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Table 8-221 LUT3_11_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.52 LUT3_11_CFG3 Register (Offset = 366h) [Reset = X0h]

LUT3_11_CFG3 is shown in Table 8-222.

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Table 8-222 LUT3_11_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.53 LUT3_11_CFG4 Register (Offset = 367h) [Reset = XXh]

LUT3_11_CFG4 is shown in Table 8-223.

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Table 8-223 LUT3_11_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

8.3.54 LUT3_12_CFG0 Register (Offset = 368h) [Reset = X0h]

LUT3_12_CFG0 is shown in Table 8-224.

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Table 8-224 LUT3_12_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.55 LUT3_12_CFG1 Register (Offset = 369h) [Reset = X0h]

LUT3_12_CFG1 is shown in Table 8-225.

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Table 8-225 LUT3_12_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.56 LUT3_12_CFG2 Register (Offset = 36Ah) [Reset = X0h]

LUT3_12_CFG2 is shown in Table 8-226.

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Table 8-226 LUT3_12_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.57 LUT3_12_CFG3 Register (Offset = 36Bh) [Reset = X0h]

LUT3_12_CFG3 is shown in Table 8-227.

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Table 8-227 LUT3_12_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.58 LUT3_12_CFG4 Register (Offset = 36Ch) [Reset = XXh]

LUT3_12_CFG4 is shown in Table 8-228.

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Table 8-228 LUT3_12_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

8.3.59 LUT3_13_CFG0 Register (Offset = 36Dh) [Reset = X0h]

LUT3_13_CFG0 is shown in Table 8-229.

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Table 8-229 LUT3_13_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

8.3.60 LUT3_13_CFG1 Register (Offset = 36Eh) [Reset = X0h]

LUT3_13_CFG1 is shown in Table 8-230.

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Table 8-230 LUT3_13_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.61 LUT3_13_CFG2 Register (Offset = 36Fh) [Reset = X0h]

LUT3_13_CFG2 is shown in Table 8-231.

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Table 8-231 LUT3_13_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.62 LUT3_13_CFG3 Register (Offset = 370h) [Reset = X0h]

LUT3_13_CFG3 is shown in Table 8-232.

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Table 8-232 LUT3_13_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.63 LUT3_13_CFG4 Register (Offset = 371h) [Reset = XXh]

LUT3_13_CFG4 is shown in Table 8-233.

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Table 8-233 LUT3_13_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

8.3.64 CNT6_FSM0_CFG0 Register (Offset = 37Eh) [Reset = X0h]

CNT6_FSM0_CFG0 is shown in Table 8-234.

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Table 8-234 CNT6_FSM0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.65 CNT6_FSM0_CFG1 Register (Offset = 37Fh) [Reset = X0h]

CNT6_FSM0_CFG1 is shown in Table 8-235.

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Table 8-235 CNT6_FSM0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.66 CNT6_FSM0_CFG2 Register (Offset = 380h) [Reset = 0Xh]

CNT6_FSM0_CFG2 is shown in Table 8-236.

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Table 8-236 CNT6_FSM0_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.67 CNT7_FSM1_CFG0 Register (Offset = 381h) [Reset = X0h]

CNT7_FSM1_CFG0 is shown in Table 8-237.

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Table 8-237 CNT7_FSM1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.68 CNT7_FSM1_CFG1 Register (Offset = 382h) [Reset = X0h]

CNT7_FSM1_CFG1 is shown in Table 8-238.

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Table 8-238 CNT7_FSM1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.69 CNT7_FSM1_CFG2 Register (Offset = 383h) [Reset = 0Xh]

CNT7_FSM1_CFG2 is shown in Table 8-239.

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Table 8-239 CNT7_FSM1_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.70 CNT8_FSM2_CFG0 Register (Offset = 384h) [Reset = X0h]

CNT8_FSM2_CFG0 is shown in Table 8-240.

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Table 8-240 CNT8_FSM2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.71 CNT8_FSM2_CFG1 Register (Offset = 385h) [Reset = X0h]

CNT8_FSM2_CFG1 is shown in Table 8-241.

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Table 8-241 CNT8_FSM2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.72 CNT8_FSM2_CFG2 Register (Offset = 386h) [Reset = 0Xh]

CNT8_FSM2_CFG2 is shown in Table 8-242.

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Table 8-242 CNT8_FSM2_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.73 CNT9_FSM3_CFG0 Register (Offset = 387h) [Reset = X0h]

CNT9_FSM3_CFG0 is shown in Table 8-243.

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Table 8-243 CNT9_FSM3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

8.3.74 CNT9_FSM3_CFG1 Register (Offset = 388h) [Reset = X0h]

CNT9_FSM3_CFG1 is shown in Table 8-244.

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Table 8-244 CNT9_FSM3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

8.3.75 CNT9_FSM3_CFG2 Register (Offset = 389h) [Reset = 0Xh]

CNT9_FSM3_CFG2 is shown in Table 8-245.

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Table 8-245 CNT9_FSM3_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

8.3.76 PWM_GEN0_CFG Register (Offset = 38Ah) [Reset = 0Xh]

PWM_GEN0_CFG is shown in Table 8-246.

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Table 8-246 PWM_GEN0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PWM_EN	R/W	0h	PWM EN 0h = Disabled 1h = Enabled
6:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

8.3.77 PWM_GEN1_CFG Register (Offset = 38Bh) [Reset = 0Xh]

PWM_GEN1_CFG is shown in Table 8-247.

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Table 8-247 PWM_GEN1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PWM_EN	R/W	0h	PWM EN 0h = Disabled 1h = Enabled
6:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

8.3.78 PWM_GEN2_CFG Register (Offset = 38Ch) [Reset = 0Xh]

PWM_GEN2_CFG is shown in Table 8-248.

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Table 8-248 PWM_GEN2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PWM_EN	R/W	0h	PWM EN 0h = Disabled 1h = Enabled
6:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

8.3.79 PWM_GEN3_CFG Register (Offset = 38Dh) [Reset = 0Xh]

PWM_GEN3_CFG is shown in Table 8-249.

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Table 8-249 PWM_GEN3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PWM_EN	R/W	0h	PWM EN 0h = Disabled 1h = Enabled
6:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

8.3.80 PWM_SRC_CFG Register (Offset = 38Eh) [Reset = X0h]

PWM_SRC_CFG is shown in Table 8-250.

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Table 8-250 PWM_SRC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	PWM3_DATA_SEL	R/W	0h	PWM3 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3
5:4	PWM2_DATA_SEL	R/W	0h	PWM2 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3
3:2	PWM1_DATA_SEL	R/W	Xh	PWM1 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3
1:0	PWM0_DATA_SEL	R/W	Xh	PWM0 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3

8.3.81 SM_CFG0 Register (Offset = 38Fh) [Reset = XXh]

SM_CFG0 is shown in Table 8-251.

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Table 8-251 SM_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S1_IN0	R/W	Xh	STATE1 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S0_IN0	R/W	Xh	STATE0 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.82 SM_CFG1 Register (Offset = 390h) [Reset = XXh]

SM_CFG1 is shown in Table 8-252.

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Table 8-252 SM_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S1_IN1	R/W	Xh	STATE1 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S0_IN1	R/W	Xh	STATE0 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.83 SM_CFG2 Register (Offset = 391h) [Reset = 00h]

SM_CFG2 is shown in Table 8-253.

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Table 8-253 SM_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2:0	RESERVED	R	0h	Reserved

8.3.84 SM_CFG3 Register (Offset = 392h) [Reset = XXh]

SM_CFG3 is shown in Table 8-254.

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Table 8-254 SM_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S3_IN0	R/W	Xh	STATE3 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S2_IN0	R/W	Xh	STATE2 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.85 SM_CFG4 Register (Offset = 393h) [Reset = XXh]

SM_CFG4 is shown in Table 8-255.

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Table 8-255 SM_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S3_IN1	R/W	Xh	STATE3 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S2_IN1	R/W	Xh	STATE2 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.86 SM_CFG5 Register (Offset = 394h) [Reset = 00h]

SM_CFG5 is shown in Table 8-256.

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Table 8-256 SM_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2:0	RESERVED	R	0h	Reserved

8.3.87 SM_CFG6 Register (Offset = 395h) [Reset = XXh]

SM_CFG6 is shown in Table 8-257.

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Table 8-257 SM_CFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S5_IN0	R/W	Xh	STATE5 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S4_IN0	R/W	Xh	STATE4 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.88 SM_CFG7 Register (Offset = 396h) [Reset = XXh]

SM_CFG7 is shown in Table 8-258.

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Table 8-258 SM_CFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S5_IN1	R/W	Xh	STATE5 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S4_IN1	R/W	Xh	STATE4 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.89 SM_CFG8 Register (Offset = 397h) [Reset = 00h]

SM_CFG8 is shown in Table 8-259.

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Table 8-259 SM_CFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2:0	RESERVED	R	0h	Reserved

8.3.90 SM_CFG9 Register (Offset = 398h) [Reset = XXh]

SM_CFG9 is shown in Table 8-260.

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Table 8-260 SM_CFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S7_IN0	R/W	Xh	STATE7 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S6_IN0	R/W	Xh	STATE6 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.91 SM_CFG10 Register (Offset = 399h) [Reset = XXh]

SM_CFG10 is shown in Table 8-261.

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Table 8-261 SM_CFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S7_IN1	R/W	Xh	STATE7 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S6_IN1	R/W	Xh	STATE6 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.92 SM_CFG11 Register (Offset = 39Ah) [Reset = 00h]

SM_CFG11 is shown in Table 8-262.

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Table 8-262 SM_CFG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SM_SYNC_EN	R/W	0h	State machine synchronous mode clock sync enable 0h = Disabled 1h = Enabled
6:4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2:0	RESERVED	R	0h	Reserved

8.3.93 SM_CFG12 Register (Offset = 3A7h) [Reset = X0h]

SM_CFG12 is shown in Table 8-263.

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Table 8-263 SM_CFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	SM_CLK_SEL	R/W	0h	State machine CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2.048kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Previous CNT out (CNT4) Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3	MODE_SEL	R/W	Xh	State machine synchronous mode select 0h = Asynchronous 1h = Synchronous
2:0	SM_INIT_STATE	R/W	Xh	State machine initial state select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

8.3.94 SM_CFG13 Register (Offset = 3A8h) [Reset = X0h]

SM_CFG13 is shown in Table 8-264.

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Table 8-264 SM_CFG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S0_OUT_CFG	R/W	Xh

8.3.95 SM_CFG14 Register (Offset = 3A9h) [Reset = X0h]

SM_CFG14 is shown in Table 8-265.

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Table 8-265 SM_CFG14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S1_OUT_CFG	R/W	Xh

8.3.96 SM_CFG15 Register (Offset = 3AAh) [Reset = X0h]

SM_CFG15 is shown in Table 8-266.

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Table 8-266 SM_CFG15 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S2_OUT_CFG	R/W	Xh

8.3.97 SM_CFG16 Register (Offset = 3ABh) [Reset = X0h]

SM_CFG16 is shown in Table 8-267.

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Table 8-267 SM_CFG16 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S3_OUT_CFG	R/W	Xh

8.3.98 SM_CFG17 Register (Offset = 3ACh) [Reset = X0h]

SM_CFG17 is shown in Table 8-268.

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Table 8-268 SM_CFG17 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S4_OUT_CFG	R/W	Xh

8.3.99 SM_CFG18 Register (Offset = 3ADh) [Reset = X0h]

SM_CFG18 is shown in Table 8-269.

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Table 8-269 SM_CFG18 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S5_OUT_CFG	R/W	Xh

8.3.100 SM_CFG19 Register (Offset = 3AEh) [Reset = X0h]

SM_CFG19 is shown in Table 8-270.

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Table 8-270 SM_CFG19 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S6_OUT_CFG	R/W	Xh

8.3.101 SM_CFG20 Register (Offset = 3AFh) [Reset = X0h]

SM_CFG20 is shown in Table 8-271.

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Table 8-271 SM_CFG20 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S7_OUT_CFG	R/W	Xh

8.3.102 WDT_CFG0 Register (Offset = 3B8h) [Reset = X0h]

WDT_CFG0 is shown in Table 8-272.

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Table 8-272 WDT_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	WDT_TIMEOUT_DATA	R/W	Xh	WDT Timeout Period Counter DATA

8.3.103 WDT_CFG1 Register (Offset = 3B9h) [Reset = X0h]

WDT_CFG1 is shown in Table 8-273.

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Table 8-273 WDT_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	WDT_OUT_DATA	R/W	Xh	WDT Output Period Counter DATA

8.3.104 WDT_CFG2 Register (Offset = 3BAh) [Reset = 0Xh]

WDT_CFG2 is shown in Table 8-274.

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Table 8-274 WDT_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	WDT_CLK_SEL	R/W	0h	WDT CLK SEL 0h = OSC1 (25MHz) 1h = OSC1 / 4 2h = OSC1 / 8 3h = OSC1 / 64 4h = OSC1 / 512 5h = OSC0 (2kHz or 10kHz) 6h = OSC0 / 8 7h = OSC0 / 12 8h = OSC0 / 24 9h = OSC0 / 64 Ah = OSC0 / 512 Bh = OSC0 / 4096 Ch = Reserved Dh = External CLK from CMX Eh = Reserved Fh = Reserved
3	RESERVED	R	0h	Reserved
2	WDT_EN	R/W	Xh	WDT EN 0h = Disabled 1h = Enabled
1	WDT_100X_EN	R/W	Xh	WDT 100X CLK multiplier EN 0h = Disabled 1h = Enabled
0	WDT_EN_SEL	R/W	Xh	WDT EN function select 0h = Reset CNT 1h = Pause CNT

8.3.105 PFLT_CFG Register (Offset = 3BBh) [Reset = XXh]

PFLT_CFG is shown in Table 8-275.

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Table 8-275 PFLT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:4	PFLT_DLY_SEL	R/W	Xh	Programmable filter delay value select 0h = 125 ns 1h = 250 ns 2h = 375 ns 3h = 500 ns
3	PFLT_POL	R/W	Xh	Programmable filter output polarity select 0h = Non-inverted 1h = Inverted
2	RESERVED	R	0h	Reserved
1:0	PFLT_EDGE_SEL	R/W	Xh	Programmable filter edge select 0h = Rising edge 1h = Falling edge 2h = Both edge 3h = Filter

8.3.106 FLT_CFG Register (Offset = 3BDh) [Reset = 0Xh]

FLT_CFG is shown in Table 8-276.

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Table 8-276 FLT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	FLT_POL	R/W	Xh	Filter output polarity select 0h = Non-inverted 1h = Inverted
2	RESERVED	R	0h	Reserved
1:0	FLT_EDGE_SEL	R/W	Xh	Filter / Edge detect edge select 0h = Rising edge 1h = Falling edge 2h = Both edge 3h = Filter

8.3.107 OSC0_CFG0 Register (Offset = 3BEh) [Reset = XXh]

OSC0_CFG0 is shown in Table 8-277.

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Table 8-277 OSC0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	CTRL_SRC	R/W	Xh	OSC power control source select 0h = From register 1h = From CMX
5	CTRL_SEL	R/W	Xh	OSC power control polarity select 0h = Power down (High turns off OSC) 1h = Force on (High turns on OSC)
4	SRC_SEL	R/W	Xh	OSC frequency source select 0h = Internal OSC 1h = External clock (from IO7)
3:2	PDIV	R/W	Xh	OSC pre-divider select 0h = / 1 1h = / 2 2h = / 4 3h = / 8
1	FREQ_SEL	R/W	Xh	OSC frequency select 0h = 2 kHz 1h = 10 kHz
0	PWR_MODE	R/W	Xh	OSC power mode select 0h = Auto power on 1h = Force power on

8.3.108 OSC0_CFG1 Register (Offset = 3BFh) [Reset = X0h]

OSC0_CFG1 is shown in Table 8-278.

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Table 8-278 OSC0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OUT1_EN	R/W	0h	OSC OUT1 enable 0h = Disabled 1h = Enabled
6:4	OUT1_DIV	R/W	0h	OSC OUT1 secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64
3	OUT0_EN	R/W	Xh	OSC OUT0 enable 0h = Disabled 1h = Enabled
2:0	OUT0_DIV	R/W	Xh	OSC OUT0 secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64

8.3.109 OSC1_CFG0 Register (Offset = 3C0h) [Reset = X0h]

OSC1_CFG0 is shown in Table 8-279.

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Table 8-279 OSC1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SU_DLY	R/W	0h	OSC 100ns startup delay control 0h = Enabled 1h = Disabled
6	CTRL_SRC	R/W	0h	OSC power control source select 0h = From register 1h = From CMX
5	CTRL_SEL	R/W	0h	OSC power control polarity select 0h = Power down (High turns off OSC) 1h = Force on (High turns on OSC)
4	SRC_SEL	R/W	0h	OSC frequency source select 0h = Internal OSC 1h = External clock (from IN0)
3:1	PDIV	R/W	Xh	OSC pre-divider select 0h = / 1 1h = / 2 2h = / 4 3h = / 8 4h = / 12 5h = / 24 6h = / 48 7h = Reserved
0	PWR_MODE	R/W	Xh	OSC power mode select 0h = Auto power on 1h = Force power on

8.3.110 OSC1_CFG1 Register (Offset = 3C1h) [Reset = 0Xh]

OSC1_CFG1 is shown in Table 8-280.

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Table 8-280 OSC1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	OUT_EN	R/W	Xh	OSC OUT enable 0h = Disabled 1h = Enabled
2:0	OUT_DIV	R/W	Xh	OSC OUT secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64

8.3.111 OSC1_CG Register (Offset = 3C5h) [Reset = X0h]

OSC1_CG is shown in Table 8-281.

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Table 8-281 OSC1_CG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OSC1_DIV3	R/W	0h	Disable /3, /12, and /24 dividers. 0h = Divider enabled 1h = Divider disabled
6	OSC1_DIV512	R/W	0h	Disable /512 divider. 0h = Divider enabled 1h = Divider disabled
5	OSC1_DIV64	R/W	0h	Disable /64 and /512 dividers. 0h = Divider enabled 1h = Divider disabled
4	OSC1_DIV24	R/W	0h	Disable /3, /12, and /24 dividers. 0h = Divider enabled 1h = Divider disabled
3	OSC1_DIV12	R/W	Xh	Disable /3 and /12 dividers. 0h = Divider enabled 1h = Divider disabled
2	OSC1_DIV8	R/W	Xh	Disable /8, /64, and /512 dividers. 0h = Divider enabled 1h = Divider disabled
1	OSC1_DIV4	R/W	Xh	Disable /4, /8, /64, and /512 dividers. 0h = Divider enabled 1h = Divider disabled
0	OSC1_DIV2	R/W	Xh	Disable /2, /4, /8, /64, and /512 dividers. 0h = Divider enabled 1h = Divider disabled

8.3.112 MCACMP_CFG0 Register (Offset = 3CFh) [Reset = 0Xh]

MCACMP_CFG0 is shown in Table 8-282.

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Table 8-282 MCACMP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TS_INP_EN	R/W	0h	Temperature sensor input to McACMP enable 0h = Disabled 1h = Enabled
6	VCC_INP_EN	R/W	0h	VCC input to McACMP enable 0h = Disabled 1h = Enabled
5	SYNC_EN	R/W	0h	McACMP output synchronicity select 0h = Asynchronous 1h = Synchronous
4	MCS_MODE	R/W	0h	McACMP trigger mode select 0h = Level sensitive EN mode 1h = Edge sensitive EN mode
3:2	CH_EN	R/W	0h	Number of channels sampled select 0h = 1 channel 1h = 2 channels 2h = 3 channels 3h = 4 channels
1	RESERVED	R	0h	Reserved
0	MCS_EN	R/W	Xh	Sampling mode select 0h = Regular mode (single channel) 1h = Multi-channel mode

8.3.113 MCACMP_CFG1 Register (Offset = 3D0h) [Reset = 0Xh]

MCACMP_CFG1 is shown in Table 8-283.

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Table 8-283 MCACMP_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:3	RESERVED	R	0h	Reserved
2	EDGE_SEL	R/W	Xh	McACMP sampling edge select 0h = Sample on negative edge of CLK 1h = Sample on positive edge of CLK
1:0	MCS_CLK_SEL	R/W	Xh	McACMP CLK select 0h = OSC0 (2kHz or 10kHz) 1h = OSC0 / 2 2h = OSC0 / 4 3h = OSC0 / 8

8.3.114 MCACMP_CH0_CFG0 Register (Offset = 3D1h) [Reset = XXh]

MCACMP_CH0_CFG0 is shown in Table 8-284.

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Table 8-284 MCACMP_CH0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH0 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH0 input source select 0h = AIO0 1h = AIO1 2h = AIO2 (or VCC) 3h = AIO3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH0 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH0 hysteresis select 0h = 0 mV 1h = 32 mV 2h = 64 mV 3h = 192 mV

8.3.115 MCACMP_CH0_CFG1 Register (Offset = 3D2h) [Reset = XXh]

MCACMP_CH0_CFG1 is shown in Table 8-285.

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Table 8-285 MCACMP_CH0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH0 VREF select 0h = 32 mV 1h = 64 mV 2h = 96 mV 3h = 128 mV 4h = 160 mV 5h = 192 mV 6h = 224 mV 7h = 256 mV 8h = 288 mV 9h = 320 mV Ah = 352 mV Bh = 384 mV Ch = 416 mV Dh = 448 mV Eh = 480 mV Fh = 512 mV 10h = 544 mV 11h = 576 mV 12h = 608 mV 13h = 640 mV 14h = 672 mV 15h = 704 mV 16h = 736 mV 17h = 768 mV 18h = 800 mV 19h = 832 mV 1Ah = 864 mV 1Bh = 896 mV 1Ch = 928 mV 1Dh = 960 mV 1Eh = 992 mV 1Fh = 1.024 V 20h = 1.056 V 21h = 1.088 V 22h = 1.120 V 23h = 1.152 V 24h = 1.184 V 25h = 1.216 V 26h = 1.248 V 27h = 1.280 V 28h = 1.312 V 29h = 1.344 V 2Ah = 1.376 V 2Bh = 1.408 V 2Ch = 1.440 V 2Dh = 1.472 V 2Eh = 1.504 V 2Fh = 1.536 V 30h = 1.568 V 31h = 1.600 V 32h = 1.632 V 33h = 1.664 V 34h = 1.696 V 35h = 1.728 V 36h = 1.760 V 37h = 1.792 V 38h = 1.824 V 39h = 1.856 V 3Ah = 1.888 V 3Bh = 1.920 V 3Ch = 1.952 V 3Dh = 1.984 V 3Eh = 2.016 V 3Fh = External VREF

8.3.116 MCACMP_CH1_CFG0 Register (Offset = 3D6h) [Reset = XXh]

MCACMP_CH1_CFG0 is shown in Table 8-286.

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Table 8-286 MCACMP_CH1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH1 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH1 input source select 0h = AIO0 1h = AIO1 2h = AIO2 (or VCC) 3h = AIO3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH1 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH1 hysteresis select 0h = 0 mV 1h = 32 mV 2h = 64 mV 3h = 192 mV

8.3.117 MCACMP_CH1_CFG1 Register (Offset = 3D7h) [Reset = XXh]

MCACMP_CH1_CFG1 is shown in Table 8-287.

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Table 8-287 MCACMP_CH1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH1 VREF select (same options as CH0)

8.3.118 MCACMP_CH2_CFG0 Register (Offset = 3DBh) [Reset = XXh]

MCACMP_CH2_CFG0 is shown in Table 8-288.

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Table 8-288 MCACMP_CH2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH2 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH2 input source select 0h = AIO0 1h = AIO1 2h = AIO2 (or VCC) 3h = AIO3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH2 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH2 hysteresis select 0h = 0 mV 1h = 32 mV 2h = 64 mV 3h = 192 mV

8.3.119 MCACMP_CH2_CFG1 Register (Offset = 3DCh) [Reset = XXh]

MCACMP_CH2_CFG1 is shown in Table 8-289.

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Table 8-289 MCACMP_CH2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH2 VREF select (same options as CH0)

8.3.120 MCACMP_CH3_CFG0 Register (Offset = 3E0h) [Reset = XXh]

MCACMP_CH3_CFG0 is shown in Table 8-290.

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Table 8-290 MCACMP_CH3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH3 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH3 input source seelct 0h = AIO0 1h = AIO1 2h = AIO2 (or VCC) 3h = AIO3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH3 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH3 hysteresis select 0h = 0 mV 1h = 32 mV 2h = 64 mV 3h = 192 mV

8.3.121 MCACMP_CH3_CFG1 Register (Offset = 3E1h) [Reset = XXh]

MCACMP_CH3_CFG1 is shown in Table 8-291.

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Table 8-291 MCACMP_CH3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH3 VREF select (same options as CH0)

8.3.122 SER_COMM_CFG0 Register (Offset = 3F2h) [Reset = X0h]

SER_COMM_CFG0 is shown in Table 8-292.

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Table 8-292 SER_COMM_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	I2C_ADDR_SRC_SEL	R/W	0h	I2C HW address source select (bitwise) 0h = OTP 1h = IO
3	I2C_IO_LAT	R/W	Xh	I2C HW addressing IO latching select 0h = Enabled 1h = Disabled
2	I2C_RST_EN	R/W	Xh	I2C Global Reset listening select 0h = Disabled 1h = Enabled
1	I2C_EN	R/W	Xh	I2C serial communications enable select 0h = Disabled 1h = Enabled
0	SPI_EN	R/W	Xh	SPI serial communications enable select 0h = Disabled 1h = Enabled

8.3.123 SER_COMM_CFG1 Register (Offset = 3F3h) [Reset = 00h]

SER_COMM_CFG1 is shown in Table 8-293.

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Table 8-293 SER_COMM_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	I2C_ADDR_MSB	R/W	0h	I2C HW address
3:1	I2C_ADDR_LSB	R/W	0h	I2C HW address
0	RESERVED	R	0h	Reserved

8.3.124 MISC_CFG0 Register (Offset = 3F7h) [Reset = 00h]

MISC_CFG0 is shown in Table 8-294.

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Table 8-294 MISC_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO_QC	R/W	0h	GPIO quick charge control 0h = Disabled 1h = Enabled
6	CFG_RD_LCK	R/W	0h	CFG read lock control 0h = Disabled 1h = Enabled
5	CFG_WR_LCK	R/W	0h	CFG write lock control 0h = Disabled 1h = Enabled
4	OTP_WR_LCK	R/W	0h	OTP write lock control 0h = Disabled 1h = Enabled
3:2	USER_LCK	R/W	0h	USER read/write lock control 0h = R/W to all non-reserved, non-read-only registers 1h = R/W to only Counter DATA, Watchdog Timer DATA, and Pattern Generator registers 2h = R/W to only State Machine registers 3h = R/W to only Voltage Reference select registers
1:0	RESERVED	R	0h	Reserved

8.3.125 MISC_CFG1 Register (Offset = 3F8h) [Reset = 0Xh]

MISC_CFG1 is shown in Table 8-295.

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Table 8-295 MISC_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	VBG_CTRL	R/W	0h	Bandgap control
3	RESERVED	R	0h	Reserved
2:0	PREBIAS_CTRL	R/W	Xh	Prebias control 0h = Auto on for Serial Comms. only 1h = Auto on for Serial Comms., DFF, PGEN, and Shift Reg. 2h = Auto on for Serial Comms. and counters with ext. clock 3h = Force on 4h = Auto on for Serial Comms. and OSC1 5h = Auto on for Serial Comms., DFF, PGEN, Shift Reg., and OSC1 6h = Auto on for Serial Comms., PGEN, and counters with ext. clock 7h = Force off

8.3.126 MISC_CFG2 Register (Offset = 3F9h) [Reset = 0Xh]

MISC_CFG2 is shown in Table 8-296.

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Table 8-296 MISC_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0h	Reserved
0	RD_DATA_SYNC	R/W	Xh	Read data sync control 0h = Enabled 1h = Disabled

8.3.127 DEVICE_ID4 Register (Offset = 3FAh) [Reset = X0h]

DEVICE_ID4 is shown in Table 8-297.

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Table 8-297 DEVICE_ID4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID4	R	Xh	Device ID

8.3.128 DEVICE_ID5 Register (Offset = 3FBh) [Reset = X0h]

DEVICE_ID5 is shown in Table 8-298.

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Table 8-298 DEVICE_ID5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID5	R	Xh	Device ID

8.3.129 DEVICE_ID6 Register (Offset = 3FCh) [Reset = X0h]

DEVICE_ID6 is shown in Table 8-299.

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Table 8-299 DEVICE_ID6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID6	R	Xh	Device ID

8.3.130 DEVICE_ID7 Register (Offset = 3FDh) [Reset = X0h]

DEVICE_ID7 is shown in Table 8-300.

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Table 8-300 DEVICE_ID7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID7	R	Xh	Device ID

8.3.131 CRC_LSB Register (Offset = 3FEh) [Reset = X0h]

CRC_LSB is shown in Table 8-301.

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Table 8-301 CRC_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CRC_LSB	R/W	Xh	CRC LSB for 2kb OTP

8.3.132 CRC_MSB Register (Offset = 3FFh) [Reset = X0h]

CRC_MSB is shown in Table 8-302.

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Table 8-302 CRC_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CRC_MSB	R/W	Xh	CRC MSB for 2kb OTP