SCPS289B September   2024  – August 2026 TPLD1202

PRODUCTION DATA  

  1.   1
  2.   2
  3.   3
  4. 1 Features
  5. 2 Applications
  6. 3 Description
  7. 4 Pin Configuration and Functions
  8. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Supply Current Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  I2C Bus Timing Requirements
    9. 5.9  SPI Timing Requirements
    10. 5.10 Typical Characteristics
  9. 6 Parameter Measurement Information
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch With Reset/Set Macro-Cell
          1. 7.3.3.3.1 3-bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set Macro-Cell
          1. 7.3.3.5.1 4-bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing Blocks
        1. 7.3.4.1 3-bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 8-Bit Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Detector Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Oscillators
        1. 7.3.14.1 2kHz or 10kHz Selectable Frequency Oscillator
        2. 7.3.14.2 25MHz Fixed Frequency Oscillator
        3. 7.3.14.3 Oscillator Power Modes
      15. 7.3.15 Serial Communications
        1. 7.3.15.1 I2C Mode
        2. 7.3.15.2 SPI Mode
        3. 7.3.15.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP) and Programming Procedure
        3. 7.4.4.3 Intel HEX File Format
  11. 8 TPLD1202 Registers
    1. 8.1 TPLD1202_User Registers
    2. 8.2 TPLD1202_Cfg_0 Registers
    3. 8.3 TPLD1202_Cfg_1 Registers
  12. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  14. 11Revision History
  15. 12Mechanical, Packaging, and Orderable Information

7.4.4.2 One-Time Programmable Memory (OTP) and Programming Procedure

The TPLD1202 contains one-time programmable (OTP) memory bits. These memory bits retain the set values in the absence of a power supply, are used to configure the TPLD device, and can be programmed a maximum of one time. The default values for all the configuration registers in the TPLD1202 are loaded from OTP after a POR event is issued.

Procedure to temporarily set up configuration registers:

  1. After starting up the device with the desired serial communications protocol, read the DEVICE_ID from registers 0x000 and 0x001 to verify communication with the device is established

  2. Then:

    1. For SPI, send the following four frames with at least 200µs between frames: 0x9000B9, 0x90003E, 0x9000AF, 0x900058

    2. For I2C, in four write transactions, send the following with at least 500µs between transactions:

      1. Transaction 1: BYTE0 = ADDR, BYTE1 = 0x01, BYTE2 = 0xB9

      2. Transaction 2: BYTE0 = ADDR, BYTE1 = 0x01, BYTE2 = 0x3E

      3. Transaction 3: BYTE0 = ADDR, BYTE1 = 0x01, BYTE2 = 0xAF

      4. Transaction 4: BYTE0 = ADDR, BYTE1 = 0x01, BYTE2 = 0x58

  3. After the final frame is sent, wait 1ms.

  4. Verify the configuration mode has been entered correctly by reading 0x10 from register 0x400.

  5. Write 0x02 to register 0x400.

  6. Send configuration bits to 0x200 - 0x3FF.

  7. Optionally, after sending configuration bits, read commands can be used to verify the correct data was written to the device.

  8. Then:

    1. For SPI, send the following frame: 0x90004B

    2. For I2C, send the following write transaction: BYTE0 = ADDR, BYTE1 = 0x01, BYTE2 = 0x4B

  9. Lastly, write 0x00 to register 0x400 for the configuration to take effect.

  10. Device is now temporarily configured.

Note:

When temporarily configuring the TPLD with the I2C macro-cell enabled, the first four bits of the target address is set to 0000b and the next three bits comes from the configuration bits, or ADDR = [0][0][0][0][A2][A1][A0]. An OTP burn is necessary to change the first four bits, or MSB, of the target address.

To change the temporary configuration, TI recommends power cycling the device and repeating the procedure to temporarily set up the configuration registers.

Procedure to burn the OTP:

  1. If the device has been temporarily configured, power cycle the device to clear configuration registers before continuing.

  2. Follow steps 1 - 7 from the procedure to temporarily set up configuration registers.

  3. Apply VPP to the GPI pin.

  4. Write 0x01 to register 0x401 to start the OTP programming.

  5. Wait tPP for the programming to be completed.

  6. Remove VPP from the GPI pin.

  7. Device OTP is now burned.