SCPS289B September   2024  – August 2026 TPLD1202

PRODUCTION DATA  

  1.   1
  2.   2
  3.   3
  4. 1 Features
  5. 2 Applications
  6. 3 Description
  7. 4 Pin Configuration and Functions
  8. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Supply Current Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  I2C Bus Timing Requirements
    9. 5.9  SPI Timing Requirements
    10. 5.10 Typical Characteristics
  9. 6 Parameter Measurement Information
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch With Reset/Set Macro-Cell
          1. 7.3.3.3.1 3-bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set Macro-Cell
          1. 7.3.3.5.1 4-bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing Blocks
        1. 7.3.4.1 3-bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 8-Bit Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Detector Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Oscillators
        1. 7.3.14.1 2kHz or 10kHz Selectable Frequency Oscillator
        2. 7.3.14.2 25MHz Fixed Frequency Oscillator
        3. 7.3.14.3 Oscillator Power Modes
      15. 7.3.15 Serial Communications
        1. 7.3.15.1 I2C Mode
        2. 7.3.15.2 SPI Mode
        3. 7.3.15.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP) and Programming Procedure
        3. 7.4.4.3 Intel HEX File Format
  11. 8 TPLD1202 Registers
    1. 8.1 TPLD1202_User Registers
    2. 8.2 TPLD1202_Cfg_0 Registers
    3. 8.3 TPLD1202_Cfg_1 Registers
  12. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  14. 11Revision History
  15. 12Mechanical, Packaging, and Orderable Information

7.3.11 Multi-channel Analog Comparator (McACMP)

The TPLD1202 has one Multi-channel Analog comparator (McACMP) macro-cell with an integrated sampling engine. The McACMP compares two voltages (IN+ and IN-) and outputs a digital signal (OUT) indicating which is larger, a High signal for IN+ and a Low for IN-.

TPLD1202 Multi-channel Analog Comparator Block Diagram Figure 7-45 Multi-channel Analog Comparator Block Diagram

For the McACMP macro-cell to be used in a TPLD design, the power up (PUP) port needs to be connected to a logic high signal. By connecting the PUP signal coming from the connection mux, McACMP can be operated always on, always off, or switched on dynamically. When the McACMP is powered down, the output is Low.

  • PUP = 1 => ACMP is powered up.
  • PUP = 0 => ACMP is powered down.
Upon powerup, the McACMP's output remains Low, and then become valid tstart after the PUP input signal goes High.

The McACMP macro-cell has a positive input that can be connected to a variety of external sources with a selectable gain stage and voltage hysteresis before going into the analog comparator. The negative input is either created from an internal VREF or provided by way of an external source.

Table 7-21 McACMP Input Sources
Parameters

Primary source

Secondary source
IN+ source

McACMP IN0

McACMP IN1

McACMP IN2

VCC

McACMP IN3

Temp. sensor

IN+ gain: The McACMP positive input can be provided by a variety of external sources, and can also have a selectable gain stage (1X, 0.5X, 0.33X, 0.25X) before connecting to the analog comparator.

IN- voltage range: 32mV to 2.016V through the internal VREF or up to 2.016V external source.

Hysteresis: If the internal VREF is used, corresponding McACMP channels have four selectable hysteresis options: 0mV, 32mV, 64mV, and 192mV.

  • 0mV: disables the input signal hysteresis.
  • 64mV: is a +32mV and -32mV hysteresis. For VREF = 1.024V, the trigger points are 1.056V and 0.992V.
  • 128mV: is a +64mV and -64mV hysteresis. For VREF = 1.024V, the trigger points are 1.088V and 0.960V.
  • 192mV: is a +96mV and -96mV hysteresis. For VREF = 1.024V, the trigger points are 1.120V and 0.928V.
If hysteresis is desired, the internal VREF must be used. Further, hysteresis values that otherwise extends beyond the range of the VREF is limited to the minimum and maximum values available in the device. For example, if IN- = 1.984V and VHYS = ±64mV, the lower trigger point is 1.920V and the upper trigger point is 2.016V.

When only one channel is selected, the McACMP disables the sampling engine and acts as a discrete analog comparator.

In multi-channel sampling mode, the TPLD1202 can be configured to sample up to 4 channels, each with its own selectable gain, voltage reference, and hysteresis (if the internal VREF is used). The sampling clock can be selected from the output of OSC0 with a given pre-divider and an additional divider at the McACMP. Other configurations that can be set are the output synchronicity, the trigger to begin a sample sequence, and an asynchronous reset option per channel.

When sampling in multi-channel mode, the McACMP samples the set channels in sequential order (channel 0 through channel n) and the edge of the clock on which samples are captured can be selected.

Clock: The McACMP sampling clock can be selected to be OSC0, OSC0/2, OSC0/4, or OSC0/8.

Enable trigger: Note that the Enable signal is a synchronous signal for the McACMP, thus the trigger pulse width needs to be at least one clock cycle wide.

  • Edge sensitive EN mode: The McACMP begins one sampling sequence when a rising edge is detected at the PUP input and then enter an idle state.

  • Level sensitive EN mode: The McACMP begins the sampling sequence when a high signal is detected at the PUP input and continuously sample as long as PUP is high, and once PUP goes low, the McACMP finishes the sampling sequence before entering an idle state.

Output synchronicity:

  • Simultaneous: Sampled outputs are latched and then appear at the respective channel output after the last channel is sampled.

  • Staggered: Sampled outputs appears at the respective channel output as they are sampled.

Sampling edge select:

  • Negative edge: samples are captured on the negative or falling edge of the clock.

  • Positive edge: samples are captured on the positive or rising edge of the clock.

Sequence restart/output latch reset: while the McACMP is running, a restart/reset signal can be asserted to restart the sampling sequence from channel 0. Channels can also independently be selected to have the output latch data cleared when this signal is asserted. If the reset input is held low, the McACMP will continuously sample channel 0 regardless of Enable trigger mode, until the reset is released.

There is also a data ready output that asserts a high signal for one clock of the base clock frequency once all channels configured have been sampled. For example, if the 1kHz (2kHz/2) sampling clock is selected, the data ready pulse width is 500µs.