SCPS301A September   2024  – July 2025 TPLD801-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-Cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Edge Detector Mode
        3. 7.3.4.3 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-Cell
      6. 7.3.6 Selectable Frequency Oscillator
        1. 7.3.6.1 Oscillator Power Modes
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
        1. 7.4.1.1 GPIO Quick Charge
        2. 7.4.1.2 Initialization
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.3.5 3-Bit LUT or Pipe Delay Macro-Cell

This macro-cell can serve as either a 3-bit LUT or as a pipe delay.

TPLD801-Q1 3-bit LUT or Pipe delay block diagram Figure 7-6 3-bit LUT or Pipe delay block diagram

When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection mux and produces a single output, which goes back into the connection mux. These LUTs can be configured to any 3-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV.

Table 7-11 shows the truth table for a 3-bit LUT.

Table 7-10 3-bit LUT Truth Table
IN2 IN1 IN0 OUT
0 0 0

User defined
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Each 3-bit LUT has 8 bits in the OTP to define their output function.

When used to implement a pipe delay, the three input signals from the connection mux go to the delay input (IN), clock (CLK), and reset (nRST) inputs for the flip-flop or latch, with two outputs going back to the connection mux. With this macro-cell, users can select the number of delay stages per output (from 1 to 8) and the output polarity for OUT1.

The pipe delay is an 8-stage delay composed of 8 DFFs. The DFF cells are tied in series where the output of each delay cell goes to the next DFF cell. There are delay output points for each set of the OUT0 and OUT1 outputs to a mux that is used to control the selection of the amount of delay for each pipe delay output.

For normal pipe delay functionality, the nRST input should be high. If nRST input is low, the pipe delay macro-cell is in a reset state and all outputs are low.

Figure 7-7 shows an example of the pipe delay macro-cell with 2 stages of delay selected.

TPLD801-Q1 Pipe Delay Macro-Cell Timing Example (Delay = 2) Figure 7-7 Pipe Delay Macro-Cell Timing Example (Delay = 2)