SCPS301A September   2024  – July 2025 TPLD801-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-Cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Edge Detector Mode
        3. 7.3.4.3 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-Cell
      6. 7.3.6 Selectable Frequency Oscillator
        1. 7.3.6.1 Oscillator Power Modes
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
        1. 7.4.1.1 GPIO Quick Charge
        2. 7.4.1.2 Initialization
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Supply and Power-on Reset
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.65V to 5.5V 1.04 1.30 1.50 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 1.65V to 5.5V 0.98 1.25 1.33 V
tSU Startup time from VCC rising past VPORR 1.65V to 5.5V 170 µs
VPP Programming voltage 1.65V to 5.5V 7.5 8 V
Digital IO
VT+ Positive-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.15V 0.92 1.29 V
3.3V ± 0.3V 1.55 2.17
5V ± 0.5V 2.21 3.19
VT- Negative-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.15V 0.56 0.96 V
3.3V ± 0.3V 1.10 1.79
5V ± 0.5V 1.63 2.70
VHYS Schmitt trigger hysteresis (VT+ − VT−) Logic Input with Schmitt Trigger 1.8V ± 0.15V 0.23 0.49 V
3.3V ± 0.3V 0.33 0.54
5V ± 0.5V 0.42 0.66
VOH High-level output voltage Push-pull 1X or Open-drain PMOS 1X IOH = -100µA 1.8V ± 0.15V 1.62 V
Push-pull 2X or Open-drain PMOS 2X 1.63
Push-pull 1X or Open-drain PMOS 1X IOH = -3mA 3.3V ± 0.3V 2.60 V
Push-pull 2X or Open-drain PMOS 2X 2.75
Push-pull 1X or Open-drain PMOS 1X IOH = -5mA 5V ± 0.5V 3.99 V
Push-pull 2X or Open-drain PMOS 2X 4.16
VOL Low-level output voltage Push-pull 1X IOL = 100µA 1.8V ± 0.15V 0.01 V
Push-pull 2X 0.01
Open-drain NMOS 1X 0.01
Open-drain NMOS 2X 0.01
Push-pull 1X IOL = 3mA 3.3V ± 0.3V 0.12 V
Push-pull 2X 0.08
Open-drain NMOS 1X 0.12
Open-drain NMOS 2X 0.08
Push-pull 1X IOL = 5mA 5V ± 0.5V 0.14 V
Push-pull 2X 0.10
Open-drain NMOS 1X 0.14
Open-drain NMOS 2X 0.10
II Input leakage current All pins VI = VCC 1.65V to 5.5V ±1 µA
VI = GND 1.65V to 5.5V ±1
IOZ Off-state (high-Z state) output current IO3 VO = 0 to 5.5V 0.06 µA
FOUT Max output frequency (1) Push-pull 1X or Push-pull 2X CL = 15pF 1.8V ± 0.15V 5 MHz
3.3V ± 0.3V 12
5V ± 0.5V 12
Rpu(int) Internal pull-up resistance 1 MΩ
100 kΩ
10 kΩ
Rpd(int) Internal pull-down resistance 1 MΩ
100 kΩ
10 kΩ
Rpd(int)_GPI Internal pull-down resistance (IN0) 1 MΩ
100 kΩ
20 kΩ
CI Input pin capacitance each input pin VI = VCC or GND 1.65V to 5.5V 3.2 pF
CIO Input-output pin capacitance each I/O pin VIO = VCC or GND 1.65V to 5.5V 4.0 pF
(1) Open drain switching performance will be limited by pull-up resistors used