SCPS301A September   2024  – July 2025 TPLD801-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-Cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Edge Detector Mode
        3. 7.3.4.3 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-Cell
      6. 7.3.6 Selectable Frequency Oscillator
        1. 7.3.6.1 Oscillator Power Modes
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
        1. 7.4.1.1 GPIO Quick Charge
        2. 7.4.1.2 Initialization
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)

The counters/delay generators are 8-bit, supporting counter data values from 1 to 255. For flexibility, the clock source for each of these macro-cells can be configured as the internal oscillator, a divided clock derived from an oscillator (OSC/4, /12, /24, /64, /4096), or an external clock source coming from the connection mux. There is also the option to chain from the output of the previous CNT/DLY macro-cell to implement longer counter/delay circuits. Note that the counter/delay macro-cell is rising edge triggered, that is the counter will increment/decrement on rising clock edges.

TPLD801-Q1 CNT/DLY Block Diagram Figure 7-9 CNT/DLY Block Diagram
TPLD801-Q1 CNT/DLY3 Block Diagram Figure 7-10 CNT/DLY3 Block Diagram

As a counter/delay (CNT/DLY) macro-cell, users may select from the following modes: delay, counter.

CNT/DLY3, when in Delay mode, also has an optional edge detector that will generate a short pulse on the specified edge in addition to the delayed output.