SDAA028 June   2025 MSPM0C1104 , MSPM0C1105 , MSPM0C1106 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to MSPM0 Timer Capture and Compare Module
  5. 2Implementations for Capturing 0% or 100% Duty Cycle
    1. 2.1 Application Conditions
    2. 2.2 Implementation Introduction
      1. 2.2.1 Use COMP Detect High or Low
      2. 2.2.2 Use ADC Detect High and Low
      3. 2.2.3 Use GPIO Detect High or Low
  6. 3Demo Code Running
  7. 4Summary
  8. 5References

1 Introduction to MSPM0 Timer Capture and Compare Module

Based on the device, two types of timers are available: general-purpose timers (TIMG) and advanced control timers (TIMA). Both timers use a common timer architecture, which the capture function are the same. TIMG has up to two identical capture and compare blocks. TIMA has up to four identical capture and compare blocks present to support external or internal signals. However, TIMG14 can support up to four blocks as an exception.

Pulse width capture measures the high-time of a signal on CCP. The high time is the number of TIMCLK periods from rising edge to falling edge of the CCP input, and is useful for applications to measure the duty cycle of a PWM input signal. The counter is loaded at the positive edge and captured at the negative edge (capture event is generated).

Pulse-Width Capture Mode Figure 1-1 Pulse-Width Capture Mode

As mentioned, the MSPM0 timer relies on rising and falling edges to measure PWM duty cycles. The 0% and 100% duty cycles lack these edges so these cannot be captured directly.