SDAA028 June   2025 MSPM0C1104 , MSPM0C1105 , MSPM0C1106 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to MSPM0 Timer Capture and Compare Module
  5. 2Implementations for Capturing 0% or 100% Duty Cycle
    1. 2.1 Application Conditions
    2. 2.2 Implementation Introduction
      1. 2.2.1 Use COMP Detect High or Low
      2. 2.2.2 Use ADC Detect High and Low
      3. 2.2.3 Use GPIO Detect High or Low
  6. 3Demo Code Running
  7. 4Summary
  8. 5References

2.2 Implementation Introduction

To capture a fixed-frequency PWM duty cycle, an additional timeout timer running at the same frequency as the PWM can be used. This timer generates a timeout event when a 0% or 100% duty cycle occurs and then to detect high or low of the PWM signal.

Since the MSPM0 timer lacks an input signal state monitor register, other peripherals must be used to detect the signal state. The software flow for this application note is illustrated below:

Software Flow of Main Thread Figure 2-1 Software Flow of Main Thread
TIMER1 ISR Figure 2-2 TIMER1 ISR
TIMER3 ISR Figure 2-3 TIMER3 ISR