SDAA032 July   2025 TDA4VE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding PWM Operation on TDA4x
    1. 2.1 PWM Architecture Overview
    2. 2.2 Counter-Compare Register and Duty Cycle Control
    3. 2.3 Action Qualifier and Output Behavior
    4. 2.4 Synchronization and Update Timing
  6. 3Unintended PWM Duty Cycle from Immediate CMPA Update
  7. 4Unintended PWM Duty Cycle from Up-Down Count Mode
  8. 5Best Practice for Seamless PWM Updates for LED Dimming Control
    1. 5.1 Use Shadow Registers for Duty Cycle Updates
    2. 5.2 Select the Appropriate Counter Mode
    3. 5.3 Register Configurations for Up-count Mode Under Shadowing
  9. 6Summary
  10. 7References

4 Unintended PWM Duty Cycle from Up-Down Count Mode

In LED dimming applications using PWM, maintaining intended brightness transitions is important. However, when using the up-down count mode to generate PWM, the PWM is center aligned and this causes unintended duty cycle, consequently unintended brightness flicker or glitches can appear during duty cycle changes. Let's try to understand and analyze how this issue can happen with up-down count mode by changing the duty cycle from 20% to 80%, and also applying shadowing register update as well.

Up-down count mode uses two events from Action Qualifier (AQ) module. PWM signal can toggle when TBCNT = CMPA but this event occurs two times in one PWM period, at up-counting and at down-counting.

The following registers configuration can be used to generate 20% of PWM duty cycle in up-down count mode.

EPWM_TBPRD = 62500
EPWM_TBCTL.CTRMODE = 0x2 → Up-down count mode
EPWM_CMPA = 12500 (= 62500 x 20%)
EPWM_CMPCTL.SHDWAMODE = 0 → Shadow mode

Make 80% of PWM duty cycle by updating CMPA register as shown in the following.

EPWM_CMPA = 50000 (= 62500 x 80%)

Figure 4-1 is a PWM waveform probed by logic analyzer.

Probe PWM Changes During Updating CMPA Register in Up-Down Count ModeFigure 4-1 Probe PWM Changes During Updating CMPA Register in Up-Down Count Mode

The expectations is that duty cycle comes from 20% to 80% directly but there is 71% duty which is not intended.

Analyze PWM Duty Cycle Change From 20% to 80% in Up-Down Count ModeFigure 4-2 Analyze PWM Duty Cycle Change From 20% to 80% in Up-Down Count Mode

This is analyzed as in the following.

  • Current duty cycle is 20%.
    Equation 6. Duty = 100 × 2500025000 + 100000 = 20%
  • Software writes 50000 into CMPA register in between ① and ②.
  • CMPA register is shadowed and is updated at TBCNT = 0.
  • PWM toggles at the instance of ② when TBCNT = 0 and this makes duty cycle 71%.
    Equation 7. Duty = 100 × 6250062500 + 25000 = 71%
  • From the following PWM periods, PWM duty cycle becomes 80%.
    Equation 8. Duty =100 × 100000100000 + 25000 = 80% 

In Figure 4-2, PWM duty cycle is being changed by updating CMPA register value, and CMPA register value is updated using shadowing technique accordingly. This means that CMPA register value is updated deterministically, and this happens at the event of TBCNT is zero.

Even though shadow mode is used, PWM duty cycle is transitioning from 20%, 25% and then 80%. This is inevitable and is the nature of center-aligned PWM generation and this can cause unintended result such as LED flicker in LED dimming control application.