3 Unintended PWM Duty Cycle from Immediate CMPA Update

To change PWM duty rate, write a new value into CMPA register is necessary. There is difficulty for software to update very deterministically, so CMPA register can be updated at incorrect instance and this can cause unintended PWM duty cycle, consequently results in incorrect brightness in LED control or incorrect motor speed and torque control within a short period. To prevent unpredictable update, shadow register update is used instead of immediate register update. Let us try to understand how immediate register update can cause this issue with up-count mode by changing PWM duty rate from 20% to 80%.

Consider an up-count mode PWM configured to go HIGH at TBCNT = 0 and LOW at TBCNT = CMPA. If the CMPA register is updated during the middle of a period, the PWM output can switch to LOW earlier or later than intended in the current cycle, depending on the new CMPA value. This causes a duty cycle distortion lasting for one or more PWM periods.

The following registers configuration can be used to generate 20% of PWM duty cycle in up count mode.

EPWM_TBPRD = 62500
EPWM_TBCTL.CTRMODE = 0 → Up count mode
EPWM_CMPA = 12500 (= 62500 x 20%)
EPWM_CMPCTL.SHDWAMODE = 1 → Immediate mode

Make 80% of PWM duty cycle by updating CMPA register as shown in the following.

EPWM_CMPA = 50000 (= 62500 × 80%)

Figure 3-1 is PWM signal probed through logic analyzer.

Figure 3-1 Probe PWM Changes During Updating CMPA Register in Up Count Mode

The expectation is that the duty cycle becomes from 20% to 80% directly but there are 25% duty and 83% duty which are not intended.

Figure 3-2 Analyze PWM Duty Cycle Change From 20% to 80% in Up Count Mode

This is analyzed in the following.

• Current duty cycle is 20%.
  Equation 1. $Duty = 100 \times \frac{12500}{12500 + 50000} = 20\%$
• Software writes 50000 into CMPA register in between ① and ②.
• CMPA register value is updated immediately.
• PWM toggles at the instance of ②, and this makes duty cycle 25%.
  Equation 2. $Duty = 100 \times \frac{12500}{12500 + 37500} = 25\%$
• In following PWM period, PWM duty cycle becomes 83%.
  Equation 3. $Duty = 100 \times \frac{62500}{62500 + 12500} = 83\%$
• After two consecutive PWM periods, PWM duty cycle becomes stable with 80%.
  Equation 4. $Duty = 100 \times \frac{50000}{50000 + 62500} = 80\%$

The root cause of this behavior lies in the immediate update mode of the CMPA register. In this mode, any new value written to CMPA is used immediately — even if this occurs mid-cycle. Since the PWM logic uses the current CMPA value for compare events, a mid-period change leads to incorrect output timing. This is not a hardware bug but rather a configuration oversight. Immediate updates are valid in some cases, but for dynamic duty cycle adjustment during operation, updates are not safe.