SDAA032 July   2025 TDA4VE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding PWM Operation on TDA4x
    1. 2.1 PWM Architecture Overview
    2. 2.2 Counter-Compare Register and Duty Cycle Control
    3. 2.3 Action Qualifier and Output Behavior
    4. 2.4 Synchronization and Update Timing
  6. 3Unintended PWM Duty Cycle from Immediate CMPA Update
  7. 4Unintended PWM Duty Cycle from Up-Down Count Mode
  8. 5Best Practice for Seamless PWM Updates for LED Dimming Control
    1. 5.1 Use Shadow Registers for Duty Cycle Updates
    2. 5.2 Select the Appropriate Counter Mode
    3. 5.3 Register Configurations for Up-count Mode Under Shadowing
  9. 6Summary
  10. 7References

2.4 Synchronization and Update Timing

TDA4x allows synchronization of PWM modules using sync inputs and outputs, enabling time-coordinated behavior across multiple channels. Additionally, features such as dead-band insertion, trip-zone logic, and event triggers provide safe and responsive control in critical applications.

To avoid artifacts during dynamic operation, this is essential to:

  • Enable and correctly configure shadow registers.
  • Choose an appropriate counter mode that matches the timing expectations of the application.
  • Avoid direct writes to CMPA and CMPB when immediate mode is active unless precise timing is maintained.

Understanding these components is foundational for implementing reliable and artifact-free PWM behavior on the TDA4x platform.