SDAA032 July   2025 TDA4VE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding PWM Operation on TDA4x
    1. 2.1 PWM Architecture Overview
    2. 2.2 Counter-Compare Register and Duty Cycle Control
    3. 2.3 Action Qualifier and Output Behavior
    4. 2.4 Synchronization and Update Timing
  6. 3Unintended PWM Duty Cycle from Immediate CMPA Update
  7. 4Unintended PWM Duty Cycle from Up-Down Count Mode
  8. 5Best Practice for Seamless PWM Updates for LED Dimming Control
    1. 5.1 Use Shadow Registers for Duty Cycle Updates
    2. 5.2 Select the Appropriate Counter Mode
    3. 5.3 Register Configurations for Up-count Mode Under Shadowing
  9. 6Summary
  10. 7References

1 Introduction

In the Texas Instruments TDA4x processor family, PWM generation is typically implemented using the EPWM module, which supports a range of flexible features such as configurable counter modes, compare registers, shadow loading, and event triggering. These features are essential for real-time, high-performance control systems.

Despite the versatility, PWM can produce undesirable output behavior if not configured carefully — especially during runtime updates of the duty cycle. A common issue is the appearance of intermediate or incorrect duty cycle when the compare register (CMPA/CMPB) is updated immediately, without proper synchronization to the PWM cycle. These can result in visual flicker (for example, in LEDs), sudden torque changes (for example, in motors), or EMI spikes in sensitive applications.

In real-world designs, this is essential to make sure that updates of the duty cycle occur smoothly and without unintended transients. This can be achieved through the use of shadow registers, which defer register updates until a safe point in the PWM cycle typically at the period boundary.

This application note focuses on two specific sources of PWM artifacts and presents reliable designs optimized for the TDA4x platform:

  • Immediate update of registers related to the PWM duty cycle. The recommended design is to enable and use the shadow register mechanism, which makes sure that updates take effect synchronously with the PWM period.
  • Use of center-aligned (up-down count mode) PWM mode in applications where edge-aligned timing is expected. This mismatch can cause inconsistent behavior, particularly in applications like LED dimming that rely on rising-edge or falling-edge alignment. The recommendation is to use up-count or down-count modes for edge-aligned applications.

This application note explains those issues in detail and provides a best practice to use EPWM module for LED dimming control as an example.