SDAA032 July   2025 TDA4VE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding PWM Operation on TDA4x
    1. 2.1 PWM Architecture Overview
    2. 2.2 Counter-Compare Register and Duty Cycle Control
    3. 2.3 Action Qualifier and Output Behavior
    4. 2.4 Synchronization and Update Timing
  6. 3Unintended PWM Duty Cycle from Immediate CMPA Update
  7. 4Unintended PWM Duty Cycle from Up-Down Count Mode
  8. 5Best Practice for Seamless PWM Updates for LED Dimming Control
    1. 5.1 Use Shadow Registers for Duty Cycle Updates
    2. 5.2 Select the Appropriate Counter Mode
    3. 5.3 Register Configurations for Up-count Mode Under Shadowing
  9. 6Summary
  10. 7References

6 Summary

This application note described two important considerations for achieving seamless transitions of PWM duty cycle. Specifically, this application note explained in detail how immediate register updates such as CMPA and the use of up-down count mode (center-aligned PWM) can result in unintended PWM duty cycle depending on applications when changing PWM duty cycle at run time. To address these issues, shadow register update and up count mode were recommended by providing LED dimming control as a practical example.

By understanding and analyzing these behaviors, developers can gain deeper insight into how to configure the EPWM module appropriately based on the specific requirements of the application. This foundation enables more robust, glitch-free PWM control in real-time embedded systems.