A DC thermal analysis of the devices was performed both initially, as well as after 500 temperature cycles to observe the thermal performance of the lead frame pre- and post-temperature cycling stress. In addition, the same test was administered to a TMCS device on the standard land pattern as a baseline, as well as a thermal test of the land pattern cross when using no-clean paste. Each of these boards were subjected to 40A of DC current flowing through the lead frame for ten minutes, and then images were captured. This was long enough in all cases for devices to reach thermal equilibrium.

Figure 2-10 SOIC-10 on SOIC-10 Footprint, Time Zero, SAC Water Soluble Paste

Figure 2-11 SOIC-10 on SOIC-16 Footprint, Time Zero, SAC Water Soluble Paste

Figure 2-12 SOIC-10 on SOIC-16 Footprint, Post-500 Cycles, SAC Water Soluble Paste

Figure 2-13 SOIC-10 on SOIC-16 Footprint, Time Zero, SAC No Clean Solder

The thermal images demonstrate that the temperature of the lead frame is comparable in all tests of the boards. From the initial test to the image post-500 temperature cycles, there is a less than a 1°C change (56°C vs. 56.6°C) in the final temperature. In comparison, the baseline board of the TMCS on the footprint exhibits a final temperature of 55°C. The SOIC-10 on SOIC-16 footprint board using no clean solder paste also settled around the same temperature as the others at 56.4°C. In summary, no drastic thermal changes were observed outside of the expectations of random process variation.