SDAA161 December   2025 TMS320F280025C , TMS320F280037C , TMS320F280039C , TMS320F280041C , TMS320F280049C , TMS320F28379D , TMS320F28379S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Overview
  6. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
  7. 4EPWM Configurations
    1. 4.1 Test Results
  8. 5Summary
  9. 6References

1 Introduction

Figure 1-1 shows a typical single phase three-level I-Type inverter, named neutral point clamped (NPC) inverter. The single phase NPC inverter includes 4 FETs, such as IGBT, in series, where S1 and S4 are called outer switches, with S2 and S3 called inner switches.

Single Phase Three-Level I-Type Inverter Figure 1-1 Single Phase Three-Level I-Type Inverter

Considering the difference between positive cycle and negative cycle when tied to the grid, the general switching states of four FETs in normal operation are listed in Table 1-1.

Table 1-1 General Switching States in Normal Operation
AC Cycle Switching States
S1 S2 S3 S4
Positive Alternate switch Remaining ON Alternate switch Remaining OFF
Negative Remaining OFF Alternate switch Remaining ON Alternate switch

There are several events which lead to quick shut-down to protect the semiconductors and the system, like over current, thermal overload, and so on. Unlike immediately switching off all the FETs simultaneously in two-level inverter, for three-level inverter, make sure that the correct switch-off sequence is maintained: outer switches (S1 or S4) off first, inner switches (S2 or S3) off after a specific delay, while the inner one must be switched on firstly during the recover process. This delayed protection requirement has been a challenge for lots of UPS or solar inverter customers for a long time. Since using software algorithm causes too much delay to provide in-time protection, some customers have to use external hardware circuits, such as FPGA or CPLD, to achieve such protection logic, which increases the system cost and also the development effort.

To address this challenge, the previous application report Achieve delayed protection for three-level inverter with CLB introduced a single chip design by leveraging configurable logic block (CLB) of C2000 devices to design the additional delayed protection logic for PWM signals, but when extending from single phase to three phase inverter, no enough CLB tiles for most of C2000 devices, and extra workaround was proposed by occupying additional GPIOs.

Another application report Achieve delayed protection for three-level inverter with Type 4 EPWM proposed a creative configuration to leverage existed EPWM features instead, but similarly, when extending to a three phase inverter, additional EPWM modules are required, which is not desirable for high power systems with more EPWM modules required.

Additionally, both application reports assumed the fault events were reflected in hardware (from GPIOs or internal comparator outputs), but in actual applications, the fault event is from multiple sources, and from manual shut down command. A more flexible design is expected with less limitation on the fault events.

This application report discusses how to optimize the CLB logic to achieve the same performance but with less CLB resources. Meanwhile, this can simplify the software design and users can keep the original fault response actions regardless of different fault events. With the upgraded design, any C2000 devices with at least three CLB tiles can be used for three phase three-level inverter, including F2838xD/S, F28379D/S, F28076, F28004xC, F28003x and F28P55X.